Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch

详细信息    查看全文

• 作者：Marko S. Andjelkovi? ; Vladimir Petrovi? ; Zoran Stamenkovi?…
• 关键词：Single event transient ; Single event latchup ; SPS cell ; CMOS integrated circuits ; Circuit ; level simulation
• 刊名：Journal of Electronic Testing
• 出版年：2015
• 出版时间：June 2015
• 年：2015
• 卷：31
• 期：3
• 页码：275-289
• 全文大小：3,125 KB
• 参考文献：1.Abadir GB (2005) A device simulation and model verification of single event transients in n + -p junctions. IEEE Trans Nucl Sci 52(5):1518-523
  2.Alles M (2007) Process technology and hardening. IEEE NSREC Short Course
  3.Bauman RC (2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans Dev Mater Reliab 5:305-16View Article
  4.Bruguier G, Palau JM (1996) Single particle-induced latchup. IEEE Trans Nucl Sci 43(2):522-32
  5.Cazeaux JM, Rossi D, Omana M, Metra C, Chatterjee A (2005) On transistor level gate sizing for increased robustness to transient faults. Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS-5), pp. 23-8
  6.Choudhury MR, Zhou Q, Mohanram K (2006) Design optimization for single event upset robustness using simultaneous dual-Vdd and sizing techniques. Proc. IEEE/ACM International Conference on?Computer-Aided Design, San Jose, USA, pp. 204-09
  7.Cohen N, Sriram TS, Leland N, Moyer D, Butler S, Flatley R (1999) Soft error considerations for deep submicron CMOS circuit applications. International electron devices meeting, IEDM Technical Digest, Washington, USA
  8.Dharchoudhury A, Kang SM, Cha H, Patel JH (1994) Fast timing simulation of transient faults in digital circuits. Proc. IEEE/ACM International Conference on?Computer-Aided Design, pp. 719-26
  9.Dodd P, Massengill L (2003) Basic mechanisms and modeling of single event upset in digital microelectronics. IEEE Trans Nucl Sci 50(3):583-02View Article
  10.Edmonds LD, Barnes CE, Scheick LZ (2000) An introduction to space radiation effects on microelectronics. JPL Publication 00-6, NASA
  11.ESCC (European Space Components Coordination), Total Dose Steady State Irradiation Test Method, Specifications No. 22900. Link: www.?escies.?org .
  12.Freeman L (1996) Critical charge calculations for a bipolar SRAM cell. IBM J R&D
  13.Gadlage M (2010) Impact of temperature on single event transients in deep submicrometer bulk and silicon-on-insulator digital CMOS technologies. PhD Thesis, Faculty of the Graduate School of Vanderbilt University, Nashville, Tennessee, USA
  14.Gill B Nikolaidis M, Wolff F, Papachristou P, Garverich S (2005) An efficient BICS design for SEU detection and correction in semicondcutor memories. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE-5)
  15.Hellebrand S, Zoellin CG, Ludwig S, Coym T (2007) A refined electrical model for particle strikes and its impact on SEU prediction. Proc. 22nd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Rome, Italy.
  16.Huang RHM, Hsu DKH, Wen CHP (2015) A determinate radiation hardened technique for safety-critical CMOS designs. J Electron Test: Theory Appl 31(2):181-92
  17.Johnston AH, Hughlock BW (1990) Latchup in CMOS from single particles. IEEE Trans Nucl Sci 37(6):1886-893
  18.Johnston AH, Swift GM, Edmonds LD (1997) Latchup in integrated circuits from energetic protons. IEEE Trans Nucl Sci 44(6):2367-377
  19.Karnik T, Hazucha P, Patel J (2004) Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans Dependable Secure Comput 1(2):128-43
  20.Kauppila JS, Sternberg AL, Alles ML, Francis AM, Holmes J, Amusan OA, Massengill LW (2009) A bias-dependent single-event compact model implemented into BSIM4 and a 90 nm CMOS process design kit. IEEE Trans Nucl Sci 56(6):3152-157
  21.Lacoe RC (2003) CMOS scaling, design principles and hardening-by-design methodology. IEEE NSREC Short Course
  22.Lala?PK (2003) A single error correcting and double error detecting and coding scheme for computer memory systems. In Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, USA
  23.Leibniz Institute for High Performance Microelectronics, IHP, Frankfurt (Oder), Germany, www.?ihp-microelectronics-?com
  24.Leray JL (2007) Effects of atmospheric neutrons on devices, at Sea level and in avionics embedded systems. Microelectron Reliab 47(9-1):1827-835View Article
  25.Lima Kastensmidt F, Assis T, Ribeiro I, Wirth G, Brusamarello L, Reis R (2009) Transistor sizing and folding for radiation hardening. Radiation and Its Effects on Components and Systems (RADECS), 2009 European Conference on, Bruges, Belgium
  26.Lyons RE, Vanderkulk W (1962) The use of triple modular redundancy to improve computer reliability. IBM J Res Dev 6(2):200-09
  27.Massengill L (1993) SEU modeling and prediction techniques. IEEE NSREC Short Course
  28.Messenger GC (1982) Collection of charge on junction nodes from ion tracks. IEEE Trans Nucl Sci 29(6):2024-031
  29.Narasimhan B, Bhuva BL, Schrimpf RD, Massengill LW, Gadlage MJ, Amusan OA, Holman WT, Witulski AF, Robinson WH, Black JD, Benedetto JM, Eaton PA, (2007) Characterization of digital single event transient pulse widths in 130 nm and 90 nm CMOS Technologies. IEEE Trans Nucl Sci 54(6)
  30.Nashiyama I, Hi
• 作者单位：Marko S. Andjelkovi? (1)
  Vladimir Petrovi? (2)
  Zoran Stamenkovi? (2)
  Goran S. Risti? (1)
  Goran S. Jovanovi? (1)
  
  1. Faculty of Electronic Engineering, University of Ni?, Ni?, Serbia
  2. IHP GmbH, Frankfurt (Oder), Germany
  
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems
  Electronic and Computer Engineering
  Computer-Aided Engineering and Design
  
• 出版者：Springer Netherlands
• ISSN：1573-0727

文摘

The circuit-level simulation analysis of the single event transient response of an on-chip single event latchup protection switch (SPS cell), previously designed and developed in the IHP 250?nm CMOS process, is presented. The SPS cell provides the latchup protection for standard cells on the principle of power domain control. It is based on a sensing/driving PMOS transistor which acts both as a latchup sensor and a driver for the standard cells, and includes additional PMOS and NMOS transistors for controlling the sensing/driving transistor and interfacing to the external control logic. The previous work has confirmed the SPS cell’s functionality in the case of single event latchup, and the experimental investigation has proven that the SPS cell is immune to single event latchup for LET values up to 74.8?MeV?cm2/mg. This case study extends the previous research by introducing the circuit-level simulation of the SPS cell’s response to the single event transients (SETs). Using the square pulse current as a SET model, the amplitude and duration of the SET-induced voltage pulses at the SPS cell’s outputs have been analyzed with respect to the injected charge, operating temperature, supply voltage, load (number of standard cells connected to the SPS cell) and sensing/driving transistor’s channel width. The results have shown that the immunity of the SPS cell to SETs can be significantly enhanced by connecting a larger number of standard cells to the SPS cell and increasing the sensing/driving transistor’s size, without any area overhead. An analytical expression for calculating the critical charge in terms of the transistor size and the number of standard cells connected to the SPS cell has been derived. Moreover, the SPS cell can be used as a SET sensor for detecting the levels of injected charge which cannot be mitigated by the increase of transistor size and load, and in conjunction with the external control logic it could be possible to measure the SET duration and perform online corrections of the SET-induced faults in the standard cells supplied by the SPS cell.