De-blocking Filter Design for HEVC and H.264/AVC

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• 作者：Muchen Li (20)
  Jinjia Zhou (20)
  Dajiang Zhou (20)
  Xiao Peng (20)
  Satoshi Goto (20)
  
• 关键词：HEVC ; H.264/AVC ; De ; blocking filter ; dual ; standard ; Low Power ; SHV ; HD
• 刊名：Lecture Notes in Computer Science
• 出版年：2012
• 出版时间：2012
• 年：2012
• 卷：7674
• 期：1
• 页码：285-293
• 全文大小：1961KB
• 参考文献：1. Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14 496-10 AVC. Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050 (2003)
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  16. Zhou, D., Zhou, J., Zhu, J., Liu, P., Goto, S.: A 2Gpixel/s H.264/AVC HP/MVC Video Decoder Chip for Super Hi-Vision and 3DTV/FTV Applications. ISSCC Dig. Tech. Papers, pp. 224-25 (2012)
  
• 作者单位：Muchen Li (20)
  Jinjia Zhou (20)
  Dajiang Zhou (20)
  Xiao Peng (20)
  Satoshi Goto (20)
  
  20. The Graduate School of Information, Production and Systems, Waseda University, Japan
  
• ISSN：1611-3349

文摘

As the successor of H.264/AVC, HEVC inherits the basic property of H.264/AVC and gives some new features. This paper introduces a novel dual-standard de-blocking filter architecture which could support both of the HEVC and H.264/AVC standards. It takes 48 clock cycles for H.264/AVC and 24 cycles for HEVC for every 16×16 block. The proposed unified-cross based processing order greatly reduces the design complexity. The proposed architecture occupies 43.3k equivalent gate count at frequency of 200MHz in SMIC 65nm library, which could satisfy the throughput requirement of quad-full high definition (QFHD) on 60fps for H.264/AVC and super hi-vision (SHV) on 60fps for HEVC. In addition, the total power consumption could be reduced by 37.8% in skipping mode when the edges need not be filtered.