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Design of a 1.1?GSps 12?bit digital to analog convertor with 56?dBc SFDR at Nyquist frequency
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  • 作者:Lei Zhou (1)
    Danyu Wu (1)
    Fan Jiang (1)
    Jin Wu (1)
    Zhi Jin (1)
    Xinyu Liu (1)
  • 关键词:Digital ; to ; analog converter (DAC) ; Spurious free dynamic range (SFDR) ; Wide ; band ; GaAs HBT
  • 刊名:Analog Integrated Circuits and Signal Processing
  • 出版年:2013
  • 出版时间:February 2013
  • 年:2013
  • 卷:74
  • 期:2
  • 页码:491-498
  • 全文大小:821KB
  • 参考文献:1. Van de Sande, F., Lugil, N., Demarsin, F., et al. (2012). A 7.2 GSa/s, 14 bit or 12 GSa/s, 12 bit signal generator on a chip in a 165?GHz fT BiCMOS process. / IEEE Journal of Solid-State Circuit, / 47(4), 1003-290. CrossRef
    2. Choe, M. J., Baek, K. H., & Teshome, M. (2005). A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation. / IEEE Journal of Solid-State Circuit, / 40(12), 2456-468. CrossRef
    3. Lin, C., & Bult, K. (1998). A 10-b, 500-Msamples/s CMOS in 0.6?mm2. / IEEE Journal of Solid-State Circuit, / 33(12), 1948-958. CrossRef
    4. Razavi, B. (1995). / Priciple of data conversion system design. New York: Wiley-IEEE Press.
    5. Lin, C. H., Van der Goes, F. M. L., Westra, J. R., et al. (2009). A 12 bit 2.9 GS/s DAC with IM3?<??0dBc beyond 1?GHz in 65?nm CMOS. / IEEE Journal of Solid-State Circuit, / 44(12), 3285-293. CrossRef
    6. Kuo, K. C., & Wu, C. W. (2011). A switching sequence for linear gradient error compensation in the DAC design. / IEEE Transactions on Circuits and Systems II: Express Briefs, / 58(8), 502-06. CrossRef
    7. Jewett, B., Liu, J., Poulton, K. (2005). A 1.2 GS/s 15 b DAC for precision signal generation. In: IEEE ISSCC Dig. Tech. Papers, pp. 110-12.
    8. Baek, K. H., Choe, M. J., Merlo, E., & Kang, S. M. (2003). 1 GS/s, 12-bit SiGe BiCMOS D/A convertor for high-speed DDFs. / Proceedings—International Symposium on Circuits and Systems, / 1, 901-04.
  • 作者单位:Lei Zhou (1)
    Danyu Wu (1)
    Fan Jiang (1)
    Jin Wu (1)
    Zhi Jin (1)
    Xinyu Liu (1)

    1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China
  • ISSN:1573-1979
文摘
High speed digital to analog convertor (DAC) is a key component in software defined radio systems, digital radars and wide band arbitrary waveform generators. In those applications, the performance of the DAC, especially the wideband dynamic range, is important in determining the system performance. In this paper we present a high speed 12 bit current steering DAC with optimized wideband performance. Theoretical analysis and optimizing strategy are present in this paper along with circuit details and measurement results. Experimental results reveal the proposed circuit is capable to operate up to 1.1?GSps. The measured spurious free dynamic range (SFDR) at low frequency is above 70?dBc at 1.1?GHz of sample rate. The SFDR is better than 56?dBc from DC to Nyquist frequency.

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