An energy-efficient high-speed CMOS hybrid comparator with reduced delay time in 40-nm CMOS process

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• 作者：Sen Huang ; Shengxi Diao ; Fujiang Lin
• 关键词：CMOS ; Delay time ; Dynamic comparator ; Energy efficient ; High speed ; Hybrid comparator ; Low power
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2016
• 出版时间：October 2016
• 年：2016
• 卷：89
• 期：1
• 页码：231-238
• 全文大小：1,120 KB
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems
  Electronic and Computer Engineering
  Signal,Image and Speech Processing
  
• 出版者：Springer Netherlands
• ISSN：1573-1979
• 卷排序：89

文摘

This paper presents a high speed CMOS hybrid comparator with reduced delay time and improved energy efficiency. The proposed hybrid comparator includes two stages with three stacked transistors which are suitable for low-voltage operation. The first dynamic amplifying stage uses PMOS input to reduce the common-mode voltage, while enhancing the positive feedback to reduce the discharging time in a low-power manner. The second quasi-dynamic latching stage uses NMOS input to gain the transconductance, thus reducing the latching time with negligible static power, while needing no additional clock signal. Therefore, the delay time and energy per conversion are both significantly reduced in the proposed hybrid comparator. Measurement results in 40-nm CMOS process show that the proposed hybrid comparator operates up to 6 GHz with 61.08-ps delay time. The power consumption is 345.9 \(\upmu \)W at 1.1-V supply, while the occupied die area is 64.5 \(\upmu \)m\(^2\) (7.5 \(\upmu \)m \(\times \) 8.6 \(\upmu \)m).