Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design

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• 作者：Carlo Sau ; Nicola Carta ; Luigi Raffo…
• 关键词：Signal processing ; Dataflow MoC ; MPEG ; RVC ; Coarse ; grained reconfigurability ; Low ; power ; Clock gating
• 刊名：The Journal of VLSI Signal Processing
• 出版年：2016
• 出版时间：March 2016
• 年：2016
• 卷：82
• 期：3
• 页码：311-329
• 全文大小：1,040 KB
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  8.Sau, C., Raffo, L., Palumbo, F., Bezati, E., Casale-Brunet, S., & Mattavelli, M. (2014). Automated Design Flow for Coarse-Grained Reconfigurable Platforms: an RVC-CAL Multi-Standard Decoder Use-Case. In International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).
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  10.Carta, N., Sau, C., Pani, D., Palumbo, F., & Raffo, L. (2013). A Coarse-Grained Reconfigurable Approach for Low-Power Spike Sorting Architectures. In IEEE/EMBS, International Conference on Neural Engineering, pp. 439–442.
  11.Carta, N., Sau, C., Palumbo, F., Pani, D., & Raffo, L. (2013). A Coarse-Grained Reconfigurable Wavelet Denoiser Exploiting the Multi-Dataflow Composer Tool. In Conference on Design and Architectures for Signal and Image Processing, pp. 141– 148.
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  14.Carta, N., Meloni, P., Tuveri, G., & Raffo, L. (2014). A custom MPSoC architecture with integrated power management for real-time neural signal decoding. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 4(2), 230–241.CrossRef
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  26.Wipliez, M., Siret, N., Carta, N., Palumbo, F., & Raffo, L. (2012). Design IP faster: Introducing the C ~high-level language. In IP-SOC: IP-Embedded System Conference and Exhibition.
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  30.Sau, C., & Palumbo, F. (2014). Automatic Generation of Dataflow-Based Reconfigurable Co-processing Units. In Conference on Design and Architectures for Signal and Image Processing.
  
• 作者单位：Carlo Sau (1)
  Nicola Carta (1)
  Luigi Raffo (1)
  Francesca Palumbo (2)
  
  1. DIEE Department of Electrical and Electronic Engineering EOLAB-Microelectronics and Bioengineering Lab, University of Cagliari (IT), Cagliari, Italy
  2. PolComIng Information Engineering Unit, University of Sassari (IT), Sassari, Italy
  
• 刊物类别：Engineering
• 刊物主题：Electrical Engineering
  Circuits and Systems
  Computer Imaging, Vision, Pattern Recognition and Graphics
  Computer Systems Organization and Communication Networks
  Signal,Image and Speech Processing
  Mathematics of Computing
  
• 出版者：Springer New York
• ISSN：1939-8115

文摘

Complexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitations. Wearable signal processing systems, for example, should provide high performance and support new generation standards without compromising their portability and their long-term usability. These constraints challenge hardware designers: early stage trade-off analysis and power management automated techniques are helpful to guarantee a reasonable time-to-market. In the field of video codec specifications, the MPEG standard known as Reconfigurable Video Coding (RVC) framework addresses functional complexity and adaptivity leveraging on the intrinsic modularity of the dataflow model of computation, but it still lacks in offering power management support. The main contribution of this work is providing an automatic early-stage power management methodology to be adopted within the MPEG-RVC context. Starting from different high-level specifications, our mapping methodology identifies directly on the high-level models disjointed homogeneous logic clock regions, where the platform resources can be enabled/disabled together without affecting the overall system performance. To extend its usability to the RVC community, we have integrated this methodology within the Multi-Dataflow Composer (MDC) tool. MDC is a tool for on-the-fly reconfigurable signal processing platforms deployment. In this paper, we extended MDC to address power-aware multi-context systems. To prove the effectiveness of our work, a coprocessor for image and video processing acceleration has been assembled. This latter has been synthesized on a 90 nm ASIC technology, where demonstrated up to 90 % of reduction in the dynamic power consumption on different dataflow-intensive applications. The coprocessor has been implemented also on FPGA, confirming, partially, the benefits of adopting the proposed methodology.