Analytic compact model of ballistic and quasi-ballistic transport for cylindrical gate-all-around MOSFET including drain-induced barrier lowering effect
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  • 作者:He Cheng (1) (3)
    Shigeyasu Uno (2) (3)
    Kazuo Nakazato (1)

    1. Department of Electrical Engineering and Computer Science
    ; Graduate School of Engineering ; Nagoya University ; Furo-cho ; Chikusa-ku ; Nagoya ; 464-8603 ; Japan
    3. JST
    ; CREST ; 5 Sanban-cho ; Chiyoda-ku ; Tokyo ; 102-0075 ; Japan
    2. Department of Electrical and Electronic Engineering
    ; Ritsumeikan University ; 1-1-1 Noji-Higashi ; Kusatsu ; Shiga ; 525-8577 ; Japan
  • 关键词:Ballistic and quasi ; ballistic transport ; Cylindrical GAA MOSFET ; Compact model ; The DIBL effect
  • 刊名:Journal of Computational Electronics
  • 出版年:2015
  • 出版时间:March 2015
  • 年:2015
  • 卷:14
  • 期:1
  • 页码:321-328
  • 全文大小:1,933 KB
  • 参考文献:1. Wu, S.-Y., Lin, C.Y., Chiang, M. C., Liaw, J.J., Cheng, J.Y., Yang, S.H., Liang, M., Miyashita, T., Tsai, C. H., Hsu, B.C., Chen, H.Y., Yamamoto, T., Chang, S.Y., Chang, V.S., Chang, C.H., Chen, J.H., Chen, H.F., Ting, K.C., Wu, Y.K., Pan, K.H., Tsui, R.F., Yao, C.H., Chang, P.R., Lien, H.M., Lee, T.L., Lee, H.M., Chang, T. Chang, R. Chen, M. Yeh, C.C. Chen, Y. H. Chiu, Y.H. Chen, H.C. Huang, Y.C., Lu, W., Chang, C.W., Tsai, M.H., Liu, C.C., Chen, K.S., Kuo, C.C., Lin, H.T., Jang, S.M., Ku, Y.: A 16nm CMOS FinFET technology for mobile SoC and computing applications, In: International Electron Device Meeting, pp. 9.1.1鈥?.1.4 (2013)
    2. Bangsaruntip, S., Balakrishnan, K., Cheng, S.-L., Chang, J., Brink, M., Lauer, I., Bruce, R. L., Engelmann, S.U., Pyzyna, A., Cohen, G.M., Gignac, L.M., Breslin, C.M., Newbury, J.S., Klaus, D.P., Majumdar, A., Sleight, J.W., Guillorn, M.A.: Density scaling with gate-all-around silicon nanowire MOSFETs for the 10nm node and beyond, In: International Electron Device Meeting, pp. 20.2.1鈥?0.2.4 (2013)
    3. International Technology Roadmap for Semiconductors.: 2009, 2011, and 2013 Edition, Table PIDS. www.itrs.net (2013)
    4. Cousin, B, Reyboz, M, Rozeau, O, Jaud, M-A, Ernst, T, Jomaah, J (2011) Unified short-channel compact model for cylindrical surrounding-gate MOSFET. Solid-State Electron. 56: pp. 40-46 CrossRef
    5. Hamid, HAE, I帽铆guez, B, Guitart, JR (2007) Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all-around-based MOSFETs. IEEE Trans. Electron Devices 54: pp. 572-579 CrossRef
    6. Hosseini, R, Fathipour, M, Faez, R (2012) Quantum simulation study of gate-all-around (GAA) silicon nanowire transistor and double gate metal oxide semiconductor field effect transistor (DG MOSFET). Int. J. Phys. Sci. 7: pp. 5054-5061
    7. Kawaura, H, Sakamoto, T (2001) Electrical transport in nano-scale silicon device. IEICE Trans. Electron. 84鈥揅: pp. 1037-1042
    8. Colinge, J-P (2004) Multiple-gate SOI MOSFETs. Solid-State Electron. 48: pp. 897-905 CrossRef
    9. Timp, G., Bude, J., Bourdelle, K.K., Garno, J., Ghetti, A., Gossmann, H., Green, M., Forsyth, G., Kim, Y., Kleiman, R., Klemens, F., Kornblit, A., Lochstampfor, C., Mansfield, W., Moccio, S., Sorsch, T., Tennant, D.M., Timp, W., Tung, R.: The ballistic nano-transistor, IEDM Tech. Dig. 55鈥?8 (1999)
    10. Lundstrom, M, Ren, Z (2002) Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans. Electron Devices 49: pp. 133-141 CrossRef
    11. Natori, K (2008) Compact modeling of ballistic nanowire MOSFETs. IEEE Trans. Electron Devices 55: pp. 2877-2885 CrossRef
    12. Natori, K, Kimura, Y, Shimizu, T (2005) Characteristics of a carbon nanotube field-effect transistor analyzed as a ballistic nanowire field-effect transistor. J. Appl. Phys. 97: pp. 034306 CrossRef
    13. Lundstrom, M (1997) Elementary scattering theory of the Si MOSFET. IEEE Electron Devices Lett. 18: pp. 361-363 CrossRef
    14. Yu, B, Lu, W-Y, Lu, H, Taur, Y (2007) Analytic charge model for surrounding-gate MOSFETs. IEEE Trans. Electron Device 54: pp. 492-496 CrossRef
    15. Jim茅nez, D, S谩enz, JJ, I帽铆gurez, B, Su帽茅, J, Marsal, LF, Pallar猫s, J (2004) Modeling of nanoscale gate-all-around MOSFESTs. IEEE Electron Devices Lett. 25: pp. 314-316 CrossRef
    16. Natori, K (2001) Scaling limit of the MOS transistor鈥揳 ballistic MOSFET. IEICE Trans. Electron E84-C 8: pp. 1029-1036
    17. Wang, J, Polizzi, E, Lundstrom, M (2004) A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation. J. Appl. Phys. 96: pp. 2192-2203 CrossRef
    18. Cheng, H, Uno, S, Numata, T, Nakazato, K (2013) Analytic compact model of ballistic and quasi-ballistic cylindrical gate-all-around metal-oxide-semiconductor field effect transistors including two subbands. Jpn. J. Appl. Phys. 52: pp. 04CN03 CrossRef
    19. Numata, T, Uno, S, Hattori, J, Mil鈥檉nikov, G, Kamakura, Y, Mori, N, Nakazato, K (2013) A self-consistent compact model of ballistic nanowire MOSFET with rectangular cross section. IEEE Trans. Electron Devices 60: pp. 856-862 CrossRef
    20. Numata, T, Uno, S, Nakazato, K, Kamakura, Y, Mori, N (2010) Analytical compact model of ballistic cylindrical nanowire metal-oxide-semiconductor field-effect-transistor. Jpn. J. Appl. Phys. 49: pp. 04DN05 CrossRef
    21. Yu, B, Wang, LQ, Yuan, Y, Asbeck, PM, Taur, Y (2008) Scaling of nanowire transistors. IEEE Trans. Electron Devices. 55: pp. 2846-2858 CrossRef
    22. Numata, T, Uno, S, Nakazato, K (2013) Circuit simulation model for ultimately-scale ballistic nanowire MOSFETs. IEICE Electron. Express 10: pp. 1-8 CrossRef
    23. Wu, Y-S, Su, P (2009) Analytical quantum-confinement model for short-channel gate-all-around MOSFETs under subthreshold region. IEEE Trans. Electron Devices 56: pp. 2720-2725 CrossRef
    24. Wu, Y-S, Su, P (2008) Sensitivity of gate-all-around nanowire MOSFETs to process variations-a comparison with multigate MOSFETs. IEEE Trans. Electron Devices. 55: pp. 3042-3047 CrossRef
    25. Riley, K.F., Hobson, M.P., Bence, S.J.: Mathematical Methods for Physics and Engineering. Cambridge University Press, Cambridge (2006)
    26. Gautam, R., Saxena, M., Gupta, R.S., Gupta, M.: Two dimensional analytical subthreshold model of nanoscale cylindrical surrounding gate MOSFET including impact of localized charges. J. Comput. Theor. Nanosci. 9(4), 602鈥?10 (2012)
    27. Cui, N, Liu, L, Xie, Q, Tan, Z, Liang, R, Wang, J, Xu, J (2013) A two-dimensional analytical model for tunnel field effect transistor and its applications. Jpn. J. Appl. Phys. 52: pp. 044303 CrossRef
    28. Electronic Archive: Atlas User鈥檚 Manual, Charpter 13, Quantum Effect Simulation, pp. 754鈥?95. Silvaco, Inc. CA. www.silvaco.com (2011)
    29. Chaudhry, A, Roy, JN (2010) Analytical modeling of source-to-drain tunneling in nanoscale silicon MOSFET. J. Electron. Sci. Technol. 8: pp. 346-350
  • 刊物类别:Engineering
  • 刊物主题:Electronic and Computer Engineering
    Optical and Electronic Materials
    Mathematical and Computational Physics
    Applied Mathematics and Computational Methods of Engineering
    Mechanical Engineering
  • 出版者:Springer Netherlands
  • ISSN:1572-8137
文摘
We propose an analytic compact model of drain current in the ballistic and quasi-ballistic modes for cylindrical gate-all-around MOSFETs incorporating drain-induced barrier lowering (DIBL) effect. The model is based on our previous work addressing an analytic compact model for all operation regions, where electrostatic potential profile along the channel has not been taken into account. In this paper, we introduce variation of electrostatic potential along the channel to model the DIBL effect in the subthreshold region. The resulting analytic compact model is tested against TCAD simulation, and good accuracy is demonstrated.

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