A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

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• 作者：Haiying Yuan ; Kun Guo ; Xun Sun ; Zijian Ju
• 关键词：Don’t care bit filling ; Test data compression ; Test power dissipation ; Area overhead ; Alternating statistical run ; length code
• 刊名：Journal of Electronic Testing
• 出版年：2016
• 出版时间：February 2016
• 年：2016
• 卷：32
• 期：1
• 页码：59-68
• 全文大小：630 KB
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• 作者单位：Haiying Yuan (1)
  Kun Guo (1)
  Xun Sun (2)
  Zijian Ju (1)
  
  1. College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing, 100124, China
  2. Department of Electronic Engineering, Tsinghua University, Beijing, 100084, China
  
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems
  Electronic and Computer Engineering
  Computer-Aided Engineering and Design
  
• 出版者：Springer Netherlands
• ISSN：1573-0727

文摘

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing. Keywords Don’t care bit filling Test data compression Test power dissipation Area overhead Alternating statistical run-length code