A 1.1 V 10-bit 62MS/s pipeline ADC with two-step non-overlapping clock generation for multi I-Q channel RF receivers

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• 作者：Hyungyu Ju ; Minjae Lee
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2016
• 出版时间：June 2016
• 年：2016
• 卷：87
• 期：3
• 页码：341-352
• 全文大小：2,882 KB
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems
  Electronic and Computer Engineering
  Signal,Image and Speech Processing
  
• 出版者：Springer Netherlands
• ISSN：1573-1979
• 卷排序：87

文摘

A multi-channel pipeline analog-to-digital converter (ADC) with two-step non-overlapping clock generation is presented. Op-amp sharing and reference buffer sharing between channels are implemented without a front-end sample-and-hold amplifier for low power consumption. The proposed clock generator can easily implement short reset phases between non-overlapping clocks to remove the memory effect from opamp sharing. The prototype 4-channel ADCs are implemented in a 0.11 μm CMOS process. The 10 bit ADC achieve 56.6 dB (9.1 bit ENOB) SNDR and 72.2 dB SFDR with 3 MHz input frequency. Each ADC slice occupies 0.4 mm2 and consumes 13 mW at 62 MS/s sampling frequency under 1.1 V supply.KeywordsPipeline ADCOp-amp sharingClock generationReference sharingSHA-less