An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order

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• 关键词：Domain ; Oriented Masking ; Private circuits ; Threshold implementations ; ISW ; Side ; channel analysis ; DPA ; Hardware security ; AES
• 刊名：Lecture Notes in Computer Science
• 出版年：2017
• 出版时间：2017
• 年：2017
• 卷：10159
• 期：1
• 页码：95-112
• 丛书名：Topics in Cryptology ?CT-RSA 2017
• ISBN：978-3-319-52153-4
• 卷排序：10159

文摘

Passive physical attacks, like power analysis, pose a serious threat to the security of digital circuits. In this work, we introduce an efficient side-channel protected Advanced Encryption Standard (AES) hardware design that is completely scalable in terms of protection order. Therefore, we revisit the private circuits scheme of Ishai et al. [13] which is known to be vulnerable to glitches. We demonstrate how to achieve resistance against multivariate higher-order attacks in the presence of glitches for the same randomness cost as the private circuits scheme. Although our AES design is scalable, it is smaller, faster, and less randomness demanding than other side-channel protected AES implementations. Our first-order secure AES design, for example, requires only 18 bits of randomness per S-box operation and 6 kGE of chip area. We demonstrate the flexibility of our AES implementation by synthesizing it up to the 15\(^{\text {th}}\) protection order.