Nanoscale circuit implementation using tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications

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• 作者：A. Bhattacharyya ; R. Ramesh
• 关键词：TMGSNW MOSFET ; RF analysis ; LNA circuit ; S ; parameters
• 刊名：Journal of Computational Electronics
• 出版年：2017
• 出版时间：March 2017
• 年：2017
• 卷：16
• 期：1
• 页码：155-161
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Appl.Mathematics/Computational Methods of Engineering; Electrical Engineering; Theoretical, Mathematical and Computational Physics; Optical and Electronic Materials; Mechanical Engineering;
• 出版者：Springer US
• ISSN：1572-8137
• 卷排序：16

文摘

In this work, the potential benefit of tri-metal gate engineered nanowire MOSFET with gate stack for analog/RF applications is developed and presented. A systematic, quantitative investigation of main figure of merit for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, \(I_{\mathrm{on}} /I_{\mathrm{off}}\) ratio, transconductance, unity-gain frequency (\(f_{\mathrm{T}}\)), maximum oscillation frequency (\(f_{\mathrm{max}}\)) providing superior RF performance as compared to single and dual-metal gate stack nanowire MOSFET. The suitability of the device for analog/RF applications is also analyzed by implementing the device in a low-noise amplifier circuit, and the S-parameter values are estimated.