A netlist-level fault-injection tool for FPGAs

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• 作者：Christian Fibich ; Peter R?ssler…
• 关键词：fault ; injection ; FPGA ; safety ; stress test ; verification ; Fehlerinjektion ; FPGA ; Safety ; Stresstest ; Verifikation
• 刊名：e & i Elektrotechnik und Informationstechnik
• 出版年：2015
• 出版时间：September 2015
• 年：2015
• 卷：132
• 期：6
• 页码：274-281
• 全文大小：921 KB
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• 作者单位：Christian Fibich (1)
  Peter R?ssler (1)
  Stefan Tauner (1)
  Herbert Taucher (2)
  Martin Matschnig (2)
  
  1. Institut für Embedded Systems, Fachhochschule Technikum Wien, H?chst?dtplatz 6, 1200, Wien, ?sterreich
  2. Corporate Technology, Research Group Electronic Design, Siemens AG ?sterreich, Siemensstra?e 90, 1210, Wien, ?sterreich
  
• 刊物类别：Engineering
• 刊物主题：Electronic and Computer Engineering
  Computer Hardware
  Software Engineering, Programming and Operating Systems
  
• 出版者：Springer Wien
• ISSN：1613-7620

文摘

A fault-injection tool can be very interesting in context to safety-critical applications, e.g., to test fault-detection and avoidance mechanisms or simply to stress an application and analyze its behavior when faults occur. In this work, a fault-injection tool is presented which can be used to instrument an FPGA design with fault-injection logic on netlist level during the implementation phase and to inject faults during runtime afterwards. The proposed approach can be smoothly integrated into an industrial FPGA tool flow, supports devices from multiple FPGA vendors and is highly configurable in order to fit to the number of available FPGA logic resources. Differences to related approaches which are applied on either HDL- and netlist-level as well as on the FPGA configuration bitstream are described. Finally, some results are presented to prove the applicability of the proposed solution. Keywords fault-injection FPGA safety stress test verification