Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors

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• 关键词：FPGA ; Soft error ; Fault injection ; HLS
• 刊名：Lecture Notes in Computer Science
• 出版年：2016
• 出版时间：2016
• 年：2016
• 卷：9625
• 期：1
• 页码：132-143
• 全文大小：2,198 KB
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• 作者单位：Jorge Tonfat (16)
  Lucas Tambara (16)
  André Santos (16)
  Fernanda Kastensmidt (16)
  
  16. Instituto de Informática – PGMICRO, Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
  
• 丛书名：Applied Reconfigurable Computing
• ISBN：978-3-319-30481-6
• 刊物类别：Computer Science
• 刊物主题：Artificial Intelligence and Robotics
  Computer Communication Networks
  Software Engineering
  Data Encryption
  Database Management
  Computation by Abstract Devices
  Algorithm Analysis and Problem Complexity
  
• 出版者：Springer Berlin / Heidelberg
• ISSN：1611-3349

文摘

SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis (HLS) is a powerful method to explore different design architectures in FPGAs. In this paper, we analyze four different design architectures implemented in a 28 nm SRAM-based FPGA under fault injection to analyze the probability of errors of them. We compare the information of essential bits provided by Xilinx with the susceptible bits obtained by fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. There is a trade-off in the number of errors classified as silent data corruption and timeout errors according to the architecture and DSP blocks usage. The proposed characterization method can be used to guide designers to select the most efficient architecture concerning the susceptibility to upsets and performance efficiency.