Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power

详细信息    查看全文

• 作者：Garo Bournoutian (17) (18)
  Alex Orailoglu (18)
  
  17. Qualcomm Technologies ; Inc. ; San Diego ; CA ; 92121 ; USA
  18. University of California ; San Diego ; La Jolla ; CA ; 92093 ; USA
  
• 关键词：Mobile ; Low ; power ; Dynamic ; Adaptive hardware ; Pipeline
• 刊名：Lecture Notes in Computer Science
• 出版年：2015
• 出版时间：2015
• 年：2015
• 卷：9017
• 期：1
• 页码：83-95
• 全文大小：866 KB
• 参考文献：1. Austin, T, Larson, E, Ernst, D (2002) SimpleScalar: An infrastructure for computer system modeling. Computer 35: pp. 59-67 CrossRef
  2. Bahar, R., Manne, S.: Power and energy reduction via pipeline balancing. In: ISCA 2001: Proceedings of the 28th Annual International Symposium on Computer Architecture, pp. 218鈥?29 (2001)
  3. Bournoutian, G., Orailoglu, A.: On-device objective-C application optimization framework for high-performance mobile processors. In: DATE 2014: Proceedings of the 2014 Design, Automation Test in Europe Conference Exhibition, pp. 85:1鈥?5:6 (2014)
  4. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: ISCA 2000: Proceedings of the 27th Annual International Symposium on Computer Architecture, pp. 83鈥?4 (2000)
  5. Buyuktosunoglu, A., Albonesi, D., Schuster, S., Brooks, D., Bose, P., Cook, P.: A circuit level implementation of an adaptive issue queue for power-aware microprocessors. In: GLSVLSI 2001: Proceedings of the 11th Great Lakes Symposium on VLSI, pp. 73鈥?8 (2001)
  6. Greenhalgh, P.: big.LITTLE processing with ARM Cortex-A15 & Cortex-A7, May 2013. http://www.arm.com/files/downloads/big_LITTLE_Final_Final.pdf
  7. Hennessy, J., Patterson, D.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Fifth edn (2011)
  8. Hu, Z., Buyuktosunoglu, A., Srinivasan, V., Zyuban, V., Jacobson, H., Bose, P.: Microarchitectural techniques for power gating of execution units. In: ISLPED 2004: Proceedings of the 2004 International Symposium on Low Power Electronics and Design, pp. 32鈥?7 (2004)
  9. Jones, T., O鈥橞oyle, M., Abella, J., Gonzalez, A.: Software directed issue queue power reduction. In: HPCA 2005: Proceedings of the 11th International Symposium on High-Performance Computer Architecture, pp. 144鈥?53 (2005)
  10. Maro, R, Bai, Y, Bahar, RI Dynamically reconfiguring processor resources to reduce power consumption in high-performance processors. In: Falsafi, B, VijayKumar, TN eds. (2001) Power-Aware Computer Systems. Springer, Heidelbergpp. 97 CrossRef
  11. Ponomarev, D., Kucuk, G., Ghose, K.: Reducing power requirements of instruction scheduling through dynamic allocation of multiple datapath resources. In: MICRO 34: Proceedings of the 34th Annual ACM/IEEE International Symposium on Microarchitecture, pp. 90鈥?01 (2001)
  12. Powell, M., Yang, S., Falsafi, B., Roy, K., Vijaykumar, T.: Gated- \({V}_{dd}\) : a circuit technique to reduce leakage in deep-submicron cache memories. In: ISLPED 2000: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, pp. 90鈥?5 (2000)
  13. SPEC: SPEC CPU2000 Benchmarks (2000). http://www.spec.org/cpu/
  
• 作者单位：Architecture of Computing Systems 篓C ARCS 2015
• 丛书名：978-3-319-16085-6
• 刊物类别：Computer Science
• 刊物主题：Artificial Intelligence and Robotics
  Computer Communication Networks
  Software Engineering
  Data Encryption
  Database Management
  Computation by Abstract Devices
  Algorithm Analysis and Problem Complexity
  
• 出版者：Springer Berlin / Heidelberg
• ISSN：1611-3349

文摘

State-of-the-art mobile smartphone and tablet processors are beginning to employ fully speculative, out-of-order architectures with deep instruction pipelines. These processors often have pipeline lengths of 24 or more stages. Furthermore, to improve high-performance ILP, these processors provide multiple parallel pipeline paths for various instruction types. These architectures provide multiple execution clusters defined by instruction type, each with its own issue queue. Instructions are dispatched to one of the appropriate issue queues, and all issue queues are then scanned in parallel to identify instructions ready for execution. The goal of such a resource-intensive architectural design is to sustain peak processor performance. Unfortunately, applications oftentimes only leverage a small subset of these robust computation resources, and the excess hardware resources still consume power while idle. This paper proposes a novel methodology that leverages the unique characteristics of the mobile ecosystem to drive hardware adaptation for a power-efficient execution pipeline microarchitecture. The proposed architecture will monitor the run-time execution behavior in order to enable only those pipeline resources that are currently needed, allowing the system to rapidly respond to changing resource demands to ensure performance is maintained while reducing power consumption. The simulation results show that processor performance is maintained while achieving a significant reduction in execution pipeline power consumption.