A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR)

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• 作者：Milena Vratonji? ; Matthew Ziegler ; George D. Gristede ; Victor Zyuban ; Thomas Mitchell ; et al.
• 关键词：Low ; power ; Optimization
• 刊名：Lecture Notes in Computer Science
• 出版年：2010
• 出版时间：2010
• 年：2010
• 卷：5953
• 期：1
• 页码：307-316
• 全文大小：420.9 KB

文摘

In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process using state-of-the-art non-linear optimization solvers and fast circuit simulators. Node switching activities and LDC are integrated into the EinsTuner framework as parameter inputs to the FPR tuning mode. In FPR mode, the power is minimized using gate width reduction with respect to power properties of the node. The FPR methodology is evaluated on next generation microprocessor circuit designs. Power reduction results are compared with the results from the existing EinsTuner tuning methodology. The results show improvement in power reduction with the FPR optimization mode.