NOR logic function of a bendable combination of tunneling field-effect transistors with silicon nanowire channels

详细信息    查看全文

• 作者：Yoonjoong Kim ; Youngin Jeon ; Minsuk Kim ; Sangsig Kim
• 关键词：silicon nanowire array ; field ; effect transistor ; tunneling ; NOR logic gate ; bendable substrate
• 刊名：Nano Research
• 出版年：2016
• 出版时间：February 2016
• 年：2016
• 卷：9
• 期：2
• 页码：499-506
• 全文大小：1,770 KB
• 参考文献：[1]Zhang, Q.; Zhao, W.; Seabaugh, A. Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett. 2006, 27, 297–300.CrossRef
  [2]Mayer, F.; Le Royer, C.; Damlencourt, J. F.; Romanjek, K.; Andrieu, F.; Tabone, C.; Previtali, B.; Deleonibus, S. Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance. In IEEE International Electron Devices Meeting, IEDM 2008, San Francisco, CA, 2008, pp. 1–5.CrossRef
  [3]Khatami, Y.; Banerjee, K. Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energyefficient digital circuits. IEEE Trans. Electron Devices 2009, 56, 2752–2761.CrossRef
  [4]Ionescu, A. M.; Riel, H. Tunnel field-effect transistors as energy-efficient electronic switches. Nature 2011, 479, 329–337.CrossRef
  [5]Appenzeller, J.; Lin, Y. M.; Knoch, J.; Chen, Z. H.; Avouris, P. Comparing carbon nanotube transistors—The ideal choice: A novel tunneling device design. IEEE Trans. Electron Devices 2005, 52, 2568–2576.CrossRef
  [6]Zhang, Q.; Fang, T.; Xing, H. L.; Seabaugh, A.; Jena, D. Graphene nanoribbon tunnel transistors. IEEE Electron Device Lett. 2008, 29, 1344–1346.CrossRef
  [7]Le, S. T.; Jannaty, P.; Luo, X.; Zaslavsky, A.; Perea, D. E.; Dayeh, S. A.; Picraux, S. T. Axial SiGe heteronanowire tunneling field-effect transistors. Nano Lett. 2012, 12, 5850–5855.CrossRef
  [8]Lee, M.; Koo, J.; Chung, E. A.; Jeong, D. Y.; Koo, Y. S.; Kim, S. Silicon nanowire-based tunneling field-effect transistors on flexible plastic substrates. Nanotechnology 2009, 20, 455201.CrossRef
  [9]Lee, M.; Jeon, Y.; Jung, J. C.; Koo, S. M.; Kim, S. Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications. Appl. Phys. Lett. 2012, 100, 253506.CrossRef
  [10]Fahad, H. M.; Hussain, M. M. High-performance silicon nanotube tunneling FET for ultralow-power logic applications. IEEE Trans. Electron Devices 2013, 60, 1034–1039.CrossRef
  [11]Jhan, Y.-R.; Wu, Y.-C.; Hung, M.-F. Performance enhancement of nanowire tunnel field-effect transistor with asymmetrygate based on different screening length. IEEE Electron Device Lett. 2013, 34, 1482–1484.CrossRef
  [12]Knoll, L.; Zhao, Q. T.; Nichau, A.; Trellenkamp, S.; Richter, S.; Schafer, A.; Esseni, D.; Selmi, L.; Bourdelle, K. K.; Mantl, S. Inverters with strained Si nanowire complementary tunnel field-effect transistors. IEEE Electron Device Lett. 2013, 34, 813–815.CrossRef
  [13]Chang, H.-Y.; Adams, B.; Chien, P. Y.; Li, J. P.; Woo, J. C. S. Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing. IEEE Trans. Electron Devices 2013, 60, 92–96.CrossRef
  [14]Lee, M.; Jeon, Y.; Son, K. S.; Shim, J. H.; Kim, S. Comparative performance analysis of silicon nanowire tunnel FETs and MOSFETs on plastic substrates in flexible logic circuit applications. Phys. Stat. Sol. (A) 2012, 209, 1350–1358.CrossRef
  [15]Seabaugh, A. C.; Zhang, Q. Low-voltage tunnel transistors for beyond CMOS logic. Proc. IEEE 2010, 98, 2095–2110.CrossRef
  [16]Lee, M.; Jeon, Y.; Moon, T.; Kim, S. Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS inverters on plastic. ACS Nano 2011, 5, 2629–2636.CrossRef
  [17]Lewis, J. Material challenge for flexible organic devices. Mater. Today 2006, 9, 38–45.CrossRef
  [18]Sierros, K. A.; Hecht, D. S.; Banerjee, D. A.; Morris, N. J.; Hu, L.; Irvin, G. C.; Lee, R. S.; Cairns, D. R. Durable transparent carbon nanotube films for flexible device components. Thin Solid Films 2010, 518, 6977–6983.CrossRef
  [19]Nagamoto, K.; Kato, K.; Naganawa, S.; Kondo, T.; Sato, Y.; Makino, H.; Yamamoto, N.; Yamamoto, T. Structural, electrical and bending properties of transparent conductive Ga-doped ZnO films on polymer substrates. Thin Solid Films 2011, 520, 1411–1415.CrossRef
  [20]Yeom, D.; Keem, K.; Kang, J.; Jeong, D. Y.; Yoon, C.; Kim, D.; Kim, S. NOT and NAND logic circuits composed of top-gate ZnO nanowire field-effect transistors with high-Al2O3 gate layers. Nanotechnology 2008, 19, 265202.CrossRef
  [21]Mongillo, M.; Spathis, P.; Katsaros, G.; Gentile, P.; De Franceschi, S. Multifunctional devices and logic gates with undoped silicon nanowires. Nano Lett. 2012, 12, 3074–3079.CrossRef
  
• 作者单位：Yoonjoong Kim (1)
  Youngin Jeon (1)
  Minsuk Kim (1)
  Sangsig Kim (1)
  
  1. Department of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul, 136-701, Republic of Korea
  
• 刊物类别：Chemistry and Materials Science
• 刊物主题：Chinese Library of Science
  Chemistry
  Nanotechnology
  
• 出版者：Tsinghua University Press, co-published with Springer-Verlag GmbH
• ISSN：1998-0000

文摘

In this study, we propose a novel combination of tunneling field-effect transistors (TFETs) with asymmetrically doped p+-i-n+ silicon nanowire (SiNW) channels on a bendable substrate. The combination of two n-channel SiNW-TFETs (NWTFETs) in parallel and two p-channel NWTFETs in series operates as a two-input NOR logic gate. The component NWTFETs with the n- and p-channels exhibit subthreshold swings (SSs) of 69 and 53 mV·dec−1, respectively, and the on/off current ratios are ~106. The NOR logic operation is sustainable and reproducible for up to 1,000 bending cycles with a narrow transition width of ~0.26 V. The mechanical bendability of the bendable NWTFETs shows that they are stable and have good fatigue properties. To the best of our knowledge, this is the first study on the electrical and mechanical characteristics of a bendable NOR logic gate composed of NWTFETs.