High Speed Energy Efficient Static Segment Adder for Approximate Computing Applications

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• 作者：R . Jothin ; C. Vasanthanayaki
• 关键词：Static segment adder ; Accuracy adjustment logic ; Significance probability ; Approximate computing ; Computational accuracy
• 刊名：Journal of Electronic Testing
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：33
• 期：1
• 页码：125-132
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems; Electrical Engineering; Computer-Aided Engineering (CAD, CAE) and Design;
• 出版者：Springer US
• ISSN：1573-0727
• 卷排序：33

文摘

Real time high quantity digital data computing design needs to achieve high performance with required accuracy range. The constraints involved with high performance are low power consumption, area efficiency and high speed. This paper proposes a design of high speed energy efficient Static Segment Adder (SSA), which improves the overall performance based on static segmentation. Accuracy Adjustment Logic (AAL) is incorporated to improve the accuracy derived from negating lower order bytes of input operands. In this paper, an integration of static segment method and accuracy adjustment logic is used to achieve computational accuracy for error tolerant applications. The proposed adder design enables to provide high speed and energy efficiency through the static segmentation method. Image enhancement operation is carried out using proposed SSA design. In this method, 99.4% overall computational accuracy for 16-bit addition even with 8-bit adder can be achieved.