Computation of Joint Timing Yield of Sequential Networks Considering Process Variations

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• 作者：Amit Goel ; Sarvesh Bhardwaj ; Praveen Ghanta ; Sarma Vrudhula
• 刊名：Lecture Notes in Computer Science
• 出版年：2007
• 出版时间：2007
• 年：2007
• 卷：4644
• 期：1
• 页码：125-137
• 全文大小：790 KB
• 刊物类别：Computer Science
• 刊物主题：Artificial Intelligence and Robotics
  Computer Communication Networks
  Software Engineering
  Data Encryption
  Database Management
  Computation by Abstract Devices
  Algorithm Analysis and Problem Complexity
  
• 出版者：Springer Berlin / Heidelberg
• ISSN：1611-3349

文摘

This paper presents a framework for estimating the timing yield of sequential networks in the presence of process variations. We present an accurate method for characterizing various parameters such as setup time, hold time, clock to output delay etc. of sequential elements in the network. Using these models and the models of interconnects gate delays, and clock skews, we perform statistical timing analysis of combinational blocks in the circuit. The result of the timing analysis is a set of constraints involving random process variables that the network has to satisfy together in order to work correctly. We compute the joint yield of all the constraints to estimate the yield of the entire network. The proposed method provides a speedup of up to 400× compared to 10000 Monte Carlo simulations with an average error of less than 1% and 5% in mean and standard deviation respectively.