A Novel Energy-Efficient Ternary Successor and Predecessor Using CNTFET

详细信息    查看全文

• 作者：Maryam Sadat Mastoori ; Farhad Razaghian
• 关键词：Carbon nanotube field ; effect transistor (CNTFET) ; Ternary logic ; Successor ; Predecessor ; Multiple ; valued logic (MVL) design
• 刊名：Circuits, Systems, and Signal Processing
• 出版年：2016
• 出版时间：March 2016
• 年：2016
• 卷：35
• 期：3
• 页码：875-895
• 全文大小：3,386 KB
• 参考文献：1.A.K. Abu El-Seoud, M. El-Banna, M.A. Hakim, On modelling and characterization of single electron transistor. Int. J. Electron. 94, 573–585 (2007)CrossRef
  2.J. Appenzeller, Carbon nanotubes for high-performance electronics—progress and prospect. Proc. IEEE 96, 201–211 (2008)CrossRef
  3.P. Balla, A. Antoniou, Low power dissipation MOS ternary logic family. IEEE J. Solid-State Circuits 19, 739–749 (1984)CrossRef
  4.G. Cho, Y.-B. Kim, F. Lombardi, M. Choi, Performance evaluation of CNFETbased logic gates, in I2MTC 2009. IEEE instrumentation and measurement technology conference, Singapore, 2009
  5.CNFET Model (Online), http://​nano.​stanford.​edu/​models
  6.J. Deng, H.-S. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region. IEEE Trans. Electron Devices 54, 3186–3194 (2007)CrossRef
  7.J. Deng, H.-S. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking. IEEE Trans. Electron Devices 54, 3195–3205 (2007)CrossRef
  8.P. Keshavarzian, K. Navi, Efficient carbon nanotube galois field. IEICE Electron. Express 6, 546–552 (2009)CrossRef
  9.Y.-B. Kim, Y.-B. Kim, F. Lombardi, A novel design methodology to optimize the speed and power of the CNTFET circuits, in Proceedings of IEEE International Midwest Symposium on Circuits and Systems, Cancun, 2009
  10.S. Lin, Y.-B. Kim, F. Lombardi, A Novel ternary logic design based on CNFET, in Proceedings of IEEE International Midwest Symposium on Circuits and Systems, Cancun, Mexico, 2009
  11.S. Lin, Y.-B. Kim, F. Lombardi, CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10, 217–225 (2011)CrossRef
  12.P. McEuen, M. Fuhrer, H. Park, Single-walled carbon nanotube electronics. IEEE Trans. Nanotechnol. 1, 78–85 (2002)CrossRef
  13.M.H. Moaiyeri, R. Chavoshisani, A. Jalali, K. Navi, O. Hashemipour, High-performance mixed-mode universal min–max circuits for nanotechnology. Circuits Syst. Signal Process. 31, 465–488 (2012)CrossRef MathSciNet
  14.M. Moaiyeri, A. Doostaregan, K. Navi, Design of energy-efficient and robust ternary circuits for nanotechnology. IET Circuits Devices Syst. 5, 285–296 (2011)CrossRef
  15.M.H. Moaiyeri, K. Navi, O. Hashemipour, Design and evaluation of CNFET-based quaternary circuits. Circuits Syst. Signal Process. 31(5), 1631–1652 (2012)CrossRef MathSciNet
  16.K. Navi, M. Rashtian, A. Khatir, P. Keshavarzian, O. Hashemipour, High speed capacitor–inverter based carbon nanotube full adder. Nanoscale Res. Lett. 5, 859–862 (2010)CrossRef
  17.K. Navi, S. Sayedsalehi, R. Farazkish, A. Rahimi, Five input majority gate, a new device for quantum-dot cellular automata. J. Comput. Theor. Nanosci. 7, 1546–1553 (2010)CrossRef
  18.A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4, 168–179 (2005)CrossRef
  19.K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. IEEE Proc. 91, 305–327 (2003)CrossRef
  20.K. You, K. Nepal, Design of a ternary static memory cell using carbon nanotube-based transistors. IET Micro Nano Lett. 6, 381–385 (2011)CrossRef
  
• 作者单位：Maryam Sadat Mastoori (1)
  Farhad Razaghian (1)
  
  1. Department of Electrical Engineering, South Tehran Branch, Islamic Azad University, Tehran, Iran
  
• 刊物类别：Engineering
• 刊物主题：Electronic and Computer Engineering
  
• 出版者：Birkh盲user Boston
• ISSN：1531-5878

文摘

This paper presents a novel design for a ternary successor and predecessor using carbon nanotube field-effect transistors (CNTFETs). The chirality of the CNTFETs is utilized for threshold voltage control. The proposed designs are simulated and examined, using Synopsys HSPICE with Standard 32 nm CNTFET technology in various situations. Simulation results demonstrate the correct and high-performance operation of the proposed circuits even in the presence of process variations. It is shown that the proposed ternary circuits achieve a significant saving in energy consumption (95.18 % for successor and 91 % for predecessor) compared with previously presented designs. Keywords Carbon nanotube field-effect transistor (CNTFET) Ternary logic Successor Predecessor Multiple-valued logic (MVL) design