Analyzing and comparing the AES architectures for their power consumption
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- 作者：Ahmet Dogan (1)
S. Berna Ors (2)
Gokay Saldamli (3) - 关键词：AES ; Low power design ; FPGA
- 刊名：Journal of Intelligent Manufacturing
- 出版年：2014
- 出版时间：April 2014
- 年：2014
- 卷：25
- 期：2
- 页码：263-271
- 全文大小：526 KB
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S. Berna Ors (2)
Gokay Saldamli (3)
1. EPFL STI IEL ESL, ELG 134 (Btiment ELG), Station 11, 1015, Lausanne, Switzerland
2. Faculty of Electrical and Electronics Engineering, Istanbul Technical University, Istanbul, Turkey
3. Department of MIS, Bogazici University, 34342, Bebek, Istanbul, Turkey - ISSN：1572-8145
文摘
It has been a decade since the block cipher Rijndael—with some minor changes—takes the name AES (Advanced Encryption Standard) and becomes the new block cipher standard of US government. Over the passed years, through deeper analysis and conducted measurements, AES has gained significant confidence for its security. Meanwhile, the sophistication in its realizations has also evolved considerably; system designers are now able to choose a suitable AES architecture tailored for their area and performance needs. Couple of years ago, the wider technological trend has shifted towards the power aware system design, hence, low power AES architectures gain importance over area and performance oriented designs. In this study, we examine and employ the low power design techniques in reducing the power consumption. These efforts allow us to come up with a slightly different architecture for s-box module. As a result, the power consumptions of AES over the Field Programmable Gate Arrays (FPGAs) are reduced. All described work and respective measurements are carried on Xilinx FPGA families and possible comparisons are made with the existing literature.