Speed-Area Optimized VLSI Architecture of Hexagonal Search Algorithm for Motion Estimation of search="http://marklogic.com/appservices/search">\(512 \times 512\) Frames

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• 作者：Rohan Mukherjee ; Baishik Biswas…
• 关键词：VLSI architecture ; FPGA ; Motion estimation ; Hexagonal search algorithm ; Novel addressing scheme
• 刊名：Circuits, Systems, and Signal Processing
• 出版年：2017
• 出版时间：February 2017
• 年：2017
• 卷：36
• 期：2
• 页码：640-657
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing; Electronics and Microelectronics, Instrumentation;
• 出版者：Springer US
• ISSN：1531-5878
• 卷排序：36

文摘

Motion estimation accounts for major part of the computational complexity of any video coding standard. In this paper, we present efficient VLSI architecture for the implementation of hexagonal search algorithm for fast motion estimation. The proposed architecture employs sequential processing of pixel data rather than parallel processing in order to reduce the hardware area substantially while achieving the real-time speed. A novel on-chip memory organization is proposed, which reduces the address generation complexity and helps improve the speed. The architecture when implemented in Verilog HDL and mapped to Virtex-5 FPGA achieves a maximum frequency of 340 MHz, while the gate count is calculated to be 3.1 K. Thus, the proposed architecture is considered suitable to be incorporated in commercial devices such as camcorders and smart phones.