Compact models and delay computation of sub-threshold interconnect circuits

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• 作者：Rohit Dhiman ; Rohit Sharma ; Rajeevan Chandel
• 关键词：Sub ; threshold ; Very large scale integration (VLSI) ; Ultra ; low power ; Interconnects ; Complementary metal ; oxide semiconductor (CMOS) ; Crosstalk
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2015
• 出版时间：July 2015
• 年：2015
• 卷：84
• 期：1
• 页码：53-65
• 全文大小：713 KB
• 参考文献：1.Agarwal, K., Sylvester, D., & Blaauw, D. (2006). Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(5), 892-01.View Article
  2.Wang, A., Calhoun, B. H., & Chandrakasan, A. P. (2006). Sub-threshold design for ultra low-power systems. New York: Springer.
  3.Calhoun, B.H., Wang, A., Chandrakasan, A. (2004) Device sizing for minimum energy operation in subthreshold circuits, in Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 95-8.
  4.Fathabadi, H. (2013). Ultra low power improved differential amplifier. Circuits, Systems, and Signal Processing, 32(2), 861-75.MathSciNet
  5.Calhoun, B. H., & Chandrakasan, A. (2005). Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE Journal of Solid-State Circuits, 40(9), 1778-786.View Article
  6.Soeleman, H., & Roy, K. (2000) Digital CMOS logic operation in the subthreshold region, in Proceedings of the ACM Great Lakes VLSI Design Symposium, USA, pp. 107-12.
  7.Bothra, S., Rogers, B., Kellam, M., & Osburn, C. M. (1993). Analysis of the effects of scaling on interconnect delay in ULSI circuits. IEEE Transactions on Electron Devices, 40(3), 591-97.View Article
  8.Ismail, Y., & Friedman, E. G. (2000). Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. IEEE Transaction on Very Large Scale Integration Systems, 8(2), 195-06.View Article
  9.Guoqing, C., & Friedman, E. G. (2006). Low power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. IEEE Transaction on Very Large Scale Integration Systems, 14(2), 161-72.View Article
  10.Gupta, S.K., Raychowdhary, A., Roy, K. (2010) in Proceedings of the IEEE Digital computation in subthreshold region for ultra low-power operation: A device-circuit-architecture codesign perspective, pp.?160-90.
  11.Anderson, J. H., & Najm, F. N. (2009). Low power programmable FPGA routing circuitry. IEEE Transaction on Very Large Scale Integration Systems, 17(8), 1048-060.View Article
  12.Kil, J., Gu, J., & Kim, C. H. (2008). A high-speed variation-tolerant interconnect technique for sub-threshold circuits using capacitive boosting. IEEE Transaction on Very Large Scale Integration Systems, 16(4), 456-65.View Article
  13.Ho, Y., Chen, H. K., & Su, C. (2012). Energy-effective sub-threshold interconnect design using high-boosting predrivers. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2(2), 307-13.View Article
  14.Nanua, M., & Blaauw D. (2007) Investigating crosstalk in sub-threshold circuits, in International Symposium on Quality Electronic Design, San Jose, pp. 639-46.
  15.Chandel, R., Sarkar, S., & Agarwal, R. P. (2007). An analysis of interconnect delay minimization by low-voltage repeater insertion. Microelectronics Journal, 38(4-), 649-55.View Article
  16.Alioto, M. (2010). Understanding DC behavior of subthreshold CMOS logic through closed-form analysis. IEEE Transactions on Circuits and Systems I, 57(7), 1597-607.View Article MathSciNet
  17.Davis, J. A., & Meindl, J. D. (2000). Compact distributed RLC models, part II: Coupled line transient expressions and peak crosstalk in multilevel networks. IEEE Transactions on Electron Devices, 47(11), 2078-087.View Article
  18.Dhiman, R., & Chandel, R. (2014). Crosstalk analysis of CMOS buffer driven interconnects for ultra-low power applications. Journal of Computational Electronics, 13(2), 360-69.View Article
  19.Predictive Technology Model (PTM), http://?ptm.?asu.?edu . Accessed 21 March 2014.
  20.Venkatesan, R., Davis, J. A., & Meindl, J. D. (2003). Compact distributed RLC interconnect models—Part III: Transients in single and coupled lines with capacitive load termination. IEEE Transactions on Electron Devices, 50(4), 1081-093.View Article
  21.Cui, J., Zhao, W., Yin, W., & Hu, J. (2012). Signal transmission analysis of multilayer graphene nano-ribbon interconnects. IEEE Transactions on Electromagnetic Compatibility, 54(1), 126-32.View Article
  22.Tang, K.T., & Friedman, E.G. (2000) Delay and power expressions characterizing a CMOS inverter driving an RLC load, in Proceedings of the IEEE Circuits and Systems Symposium, Geneva, pp. 283-86.
  
• 作者单位：Rohit Dhiman (1)
  Rohit Sharma (2)
  Rajeevan Chandel (1)
  
  1. Electronics and Communication Engineering Department, National Institute of Technology (NIT) Hamirpur, Hamirpur, 177005, Himachal Pradesh, India
  2. Department of Electrical Engineering, Indian Institute of Technology (IIT) Ropar, Punjab, 140001, India
  
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems
  Electronic and Computer Engineering
  Signal,Image and Speech Processing
  
• 出版者：Springer Netherlands
• ISSN：1573-1979

文摘

Ultra-low power designs extensively exploit the sub-threshold region of operation of Complementary metal-oxide semiconductor (CMOS) circuits. Though sub-threshold circuit operation shows huge potential towards satisfying the ultra-low power requirement, increased crosstalk and delay have become serious design challenges particularly for sub-threshold interconnects. In this paper, novel analytical time-domain models governing the output voltage and crosstalk-induced delay of CMOS gates driving coupled resistive–capacitive interconnect in sub-threshold domain are presented. Subsequently, the transient analysis of simultaneously switching two and three coupled interconnects is carried out. It is demonstrated that the modeling of driver by linear resistance can lead to about 38?% average error in the estimation of propagation delay. The numerical results illustrate that the proposed model quite accurately estimates the performance of coupled on-chip interconnects. An average error of less than 7?% is observed in estimation of waveform shape and delay.