An Efficient Zigzag Scanning and Entropy Coding Architecture Design
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- 作者：Tongbing Cui (22)
Chuang Zhu (22)
Yangang Cai (22)
Meng Li (22)
Huizhu Jia (22)
Don Xie (22)
Wen Gao (22) - 关键词：VLSI architecture ; RDO ; zigzag scan ; entropy ; AVS
- 刊名：Lecture Notes in Computer Science
- 出版年：2013
- 出版时间：2013
- 年：2013
- 卷：8294
- 期：1
- 页码：359-371
- 全文大小：225KB
- 作者单位：Tongbing Cui (22)
Chuang Zhu (22)
Yangang Cai (22)
Meng Li (22)
Huizhu Jia (22)
Don Xie (22)
Wen Gao (22)
22. National Engineering Laboratory for Video Technology, Peking University Beijing, China - ISSN：1611-3349
文摘
Rate distortion optimization (RDO) technique is the best known mode decision method in recent video coding standard, such as H.264 and AVS. However, the unbearable computational burden limits its application. According to the proposed block-level pipeline architecture of RDO-based MD, we find that zigzag scanning and entropy coding are the bottlenecks. In our paper, we firstly analyze the time consumption of the bottlenecks, and then we propose our efficient zigzag scanning and entropy coding architecture. Finally, our enhanced architecture is implemented in AVS encoder. The experimental results show that 20% throughput can be increased compared with the 4-way parallel scanning and entropy coding. With the proposed architecture, the real time RDO-based MD processing of 1080P@30fps can be supported. And our design is realized in high-level Verilog/VHDL hardware description language and implemented under SMIC 0.18μm CMOS technology with 50K logic gates and 6 KB SRAMs at 237MHZ operation frequency.