A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts

详细信息    查看全文

• 作者：Ons Mbarek (1) mbarek@unice.fr
  Alain Pegatoquet (1) pegatoquet@unice.fr
  Michel Auguin (1) auguin@unice.fr
• 关键词：Transaction Level Modeling (TLM) &#8211 ; IEEE 1801 (UPF) standard &#8211 ; power ; aware design and verification &#8211 ; power intent specification &#8211 ; assertion ; based contracts &#8211 ; power domain
• 刊名：Lecture Notes in Computer Science
• 出版年：2011
• 出版时间：2011
• 年：2011
• 卷：6951
• 期：1
• 页码：226-236
• 全文大小：544.1 KB
• 参考文献：1. Keating, M., Flynn, D., Aitken, R., Gibbons, A., Shi, K.: Low Power Methodology Manual: for System-on-Chip Design (integrated circuits and systems). Springer, Heidelberg (2007)
  2. Unified Power Format (UPF 2.0) Standard: IEEE standard for design and verification of low power integrated circuits. IEEE 1801TM (March 27, 2009)
  3. Bembaron, F., Kakkar, S., Mukherjee, R., Srivastava, A.: Low Power Verification Methodology Using UPF. In: Proc. of Design & Verification Conference & Exhibition (DVCon), San Jose, CA, pp. 228–233 (2009)
  4. Open SystemC initiative. SystemC Transaction Level Modeling Library 2.1.0 (2009), http://www.systemc.org
  5. Dhanwada, N., Lin, I.-C., Narayanan, V.: A Power Estimation Methodology for SystemC Transaction Level Models. In: 3rd IEEE/ACM/IFIP Conference on Hardaware/Software Codesign and System Synthesis, pp. 142–147 (2005)
  6. Lee, I., Kim, H., Yang, P., Yoo, S., Chung, E.-Y., Choi, K.-M., Kong, J.-T., Eo, S.-K.: PowerViP: Soc Power Estimation Framework at Transaction Level. In: 11th Asia and South Pacific Design Automation Conference (ASP-DAC), Japan, pp. 551–558 (2006)
  7. Ben Atitallah, R., Niar, S., Dekeyser, J.L.: MPSOC Power Estimation Framework at Transaction Level Modeling. In: 19th International Conference on Microelectronics (ICM), Egypt, pp. 245–248 (2007)
  8. Lebreton, H., Vivet, P.: Power Modeling in SystemC at Transaction Level, Application to a DVFS Architecture. In: Proc. of the 2008 IEEE Computer Society Annual Symposium on VLSI, France, pp. 463–466 (2008)
  9. Hazra, A.S., Mitra, A., Dasgupta, P., Pal, A., Bagchi, D., Guha, K.: Leveraging UPF-Extracted Assertions for Modeling and Formal Verification of Architectural Power Intent. In: 47th Design Automation Conference (DAC), Anaheim, CA, pp. 773–776 (2010)
  10. Trummer, C., Kirchsteiger, C.M., Weiss, R., Dalton, D., Pistaur, M.: Simulation-based Verification of Power Aware System-on-Chip Designs Using UPF IEEE 1801. In: 27th NORCHIP Conference, Trondheim, Norway, pp. 1–4 (2009)
  11. Meyer, B.: Applying “design by contract”. IEEE Computer 25, 40–51 (1992)
  12. Magic Blue Smoke blog, http://synopsysoc.org/magicbluesmoke/2008/05
• 作者单位：1. LEAT, University of Nice-Sophia Antipolis-CNRS, 250-Rue Albert Einstein, B芒timent-4, 06560 Valbonne, France
• 刊物类别：Computer Science
• 刊物主题：Artificial Intelligence and Robotics
  Computer Communication Networks
  Software Engineering
  Data Encryption
  Database Management
  Computation by Abstract Devices
  Algorithm Analysis and Problem Complexity
  
• 出版者：Springer Berlin / Heidelberg
• ISSN：1611-3349

文摘

Building efficient and correct system power management strategies relies on efficient power architecture decision-making as well as respecting structural dependencies induced by such architecture. Transaction Level Modeling allows a rapid exploration, verification and evaluation of alternative power management architectures and strategies. This paper introduces an efficient methodology for making system power decisions at Transaction-Level (TL) by adding and verifying power intent and management capabilities into TL-models. A generic framework that abstracts relevant concepts of the IEEE 1801 (UPF) standard and implements assertion-based contracts is used throughout the methodology. A TL-model example is considered to validate the methodology.