Design optimization of a CMOS RF detector

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• 作者：Nicolas Barabino ; Fernando Silveira
• 关键词：Deep ; submicron CMOS ; RF ; Detector ; Envelope detector ; Minimum detectable signal (MDS) ; System ; on ; chip (SoC) ; Built ; in ; self ; test (BiST) ; Built ; in ; self ; calibration (BiSC)
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2016
• 出版时间：December 2016
• 年：2016
• 卷：89
• 期：3
• 页码：575-583
• 全文大小：1,089 KB
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems
  Electronic and Computer Engineering
  Signal,Image and Speech Processing
  
• 出版者：Springer Netherlands
• ISSN：1573-1979
• 卷排序：89

文摘

A procedure to optimize the design of an RF detector is presented. The optimization enables to minimize the minimum detectable signal (MDS), which is beneficial for maximizing the dynamic range, as it is often desired. The optimization also enables to minimize the bias current consumption. The detector architecture is based on a half-wave MOSFET rectifier and is suitable to implement highly linear envelope detectors. The optimization uses a model based on transistor characteristics extracted from simulations. The model was validated by comparing the predicted MDS to measurements performed at 2 GHz to an RF detector on a 90 nm CMOS process.