Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

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• 作者：Sahar Sarafi ; Abu Khari Bin Aain…
• 关键词：CMOS sampling switch ; Bootstrapped NMOS switch ; Boosted PMOS switch ; Body effect
• 刊名：Circuits, Systems, and Signal Processing
• 出版年：2016
• 出版时间：March 2016
• 年：2016
• 卷：35
• 期：3
• 页码：771-790
• 全文大小：4,362 KB
• 参考文献：1.A.M. Abo, P.R. Gray, A 1.5 V, 10-bit, 14 MS/s CMOS pipeline analog-to-digital converter. 1998 Symposium on VLSI Circuits (1998)
  2.A. Abolhasani, M. Tohidi et al., A new high-speed, high-resolution open-loop CMOS sample and hold. Analog Integr. Circ. Sig. Process 78(2), 409–419 (2014)CrossRef
  3.O.A. Adeniran, A. Demosthenous, Constant-resistance CMOS input sampling switch for GSM/WCDMA high dynamic range delta/sigma modulators. IEEE Trans. Circuits Syst. I Regul. Pap. 55(10), 3234–3245 (2008)CrossRef MathSciNet
  4.M.R. Asgari, S.H. Pishgar et al., A reliable full-swing low-distortion CMOS bootstrapped sampling switch. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2011)
  5.A. Behradfar, S. Zeinolabedinzadeh et al., A clock boosting scheme for low voltage circuits. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2008)
  6.F. Centurelli, P. Monsurro et al., Design solutions for sample-and-hold circuits in CMOS nanometer technologies. IEEE Trans. Circuits Syst. II Express Briefs 56(6), 459–463 (2009)CrossRef
  7.T.B. Cho, P.R. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE J. Solid-State Circuits 30(3), 166–172 (1995)CrossRef
  8.Y. Chun-Yueh, H. Chung-Chih, A low-voltage low-distortion MOS sampling switch. IEEE International Symposium on Circuits and Systems (ISCAS), vol. 3134, pp. 3131–3134. (2005)
  9.G.K. De Teyou, H. Petit et al., Statistical analysis of harmonic distortion in a differential bootstrapped sample and hold circuit. 10th IEEE Conference on Ph. D. Research in Microelectronics and Electronics (PRIME) (2014)
  10.C.J.B. Fayomi, G.W. Roberts et al., Low-voltage CMOS analog switch for high precision sample-and-hold circuit. Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (2000)
  11.A. Galhardo, J. Goes et al., Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies. 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS) (2007)
  12.M.I. Kazim, Design of highly linear sampling switches for CMOS track-and-hold circuits, Master Thesis, Linköpings universitet, Sweden, 2006
  13.M. Keskin, A low-voltage CMOS switch with a novel clock boosting scheme. IEEE Trans. Circuits Syst. II Express Briefs 52(4), 185–188 (2005)CrossRef MathSciNet
  14.Y. Krouglov, V. Barinov et al., The advanced boost circuit for MOS analog switch. 4th IEEE International Conference on Circuits and Systems for Communications (2008), pp. 568–571
  15.W. Lei, R. Junyan et al., A high-speed high-resolution low-distortion CMOS bootstrapped switch. IEEE International Symposium on Circuits and Systems (ISCAS) (2007)
  16.F. Maloberti, F. Francesconi et al., Design considerations on low-voltage low-power data converters. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 42(11), 853–863 (1995)CrossRef
  17.T.H. Morshed, D.D. Lu et al., BSIM4v4.7 MOSFET Model (2011), http://​www-device.​eecs.​berkeley.​edu/​bsim/​Files/​BSIM4/​BSIM470/​BSIM470_​Manual.​pdf
  18.H. Movahedian, B. Sedighi et al., Wide-range single-ended CMOS track-and-hold circuit. IEICE Electron. Express 4(12), 400–405 (2007)CrossRef
  19.A.K. Ong, V.I. Prodanov et al., A method for reducing the variation in “on” resistance of a MOS sampling switch. The 2000 IEEE International Symposium on Circuits and Systems (ISCAS) (2000)
  20.B. Park, Mixed-signal ICs in nano-scale technologies: design and challenges. IEEE International Conference of Electron Devices and Solid-state Circuits (EDSSC) (2009)
  21.Y. Peng, D. Kong et al., A low-voltage sampling switch with improved linearity. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE’06) (2006)
  22.K. Sangwook, E. Greeneich, Body effect compensated switch for low voltage switched-capacitor circuits. IEEE International Symposium on Circuits and Systems (ISCAS) (2002)
  23.S.R. Sonkusale, J. Van der Spiegel, A low distortion MOS sampling circuit. IEEE International Symposium on Circuits and Systems (ISCAS) (2002)
  24.J. Steensgaard, Bootstrapped low-voltage analog switches. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems (ISCAS ’99) (1999)
  25.M. Waltari, K. Halonen, Bootstrapped switch without bulk effect in standard CMOS technology. Electron. Lett. 38(12), 555–557 (2002)CrossRef
  26.L. Wang, W.J. Yin et al., Dual-channel bootstrapped switch for high-speed high-resolution sampling. Electron. Lett. 42(22), 1275–1276 (2006)CrossRef
  27.W. Xiaofeng, L. Hongxia et al., A bootstrapped switch employing a new clock feed-through compensation technique. J Semicond. 30(12), 125007 (2009)CrossRef
  28. http://​ptm.​asu.​edu/​
  29. http://​www.​mosis.​com
  
• 作者单位：Sahar Sarafi (1)
  Abu Khari Bin Aain (1)
  Javad Abbaszadeh (2)
  
  1. Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310, Skudai, Johor, Malaysia
  2. Department of Electronic Engineering, Islamic Azad University of Urmia, Urmia, Iran
  
• 刊物类别：Engineering
• 刊物主题：Electronic and Computer Engineering
  
• 出版者：Birkh盲user Boston
• ISSN：1531-5878

文摘

Sampling switches have a dominant role in switched-capacitor circuits and analog-to-digital convertors. Since they act as input gates, their nonlinearities directly degrade the quality of the input signals. The scaling-down trend of CMOS technology and increasing demands for high-speed and power-efficient circuits pose design challenge in high-speed sampling switches for low-voltage applications. To address this issue, an optimized CMOS switch is proposed in this paper consisting of a bootstrapped NMOS switch and a boosted PMOS switch as a transmission gate. By utilizing this technique, the nonlinearity resulting from the threshold voltage variation (body effect) of NMOS switch is mitigated, considerably. To evaluate the proposed switch, it is designed in 0.18 \(\upmu \hbox {m}\) CMOS process technology. According to the obtained simulation results, this switch can achieve total harmonic distortion of \(-\)78.81 and \(-\)62.99 dB in 100 MS/s at \(V_\mathrm{dd}\) = 1 Volt and 50 MS/s at \(V_\mathrm{dd}\) = 0.8 V, respectively. Keywords CMOS sampling switch Bootstrapped NMOS switch Boosted PMOS switch Body effect