文摘
An integrated receiver consisting of RF front ends, analog baseband (BB) chain with an analog to digital converter (ADC) for a synthetic aperture radar (SAR) implemented in 130?nm CMOS technology is presented in this paper. The circuits are integrated on a single chip with a size of 10.88?mm2. The RF front end consists of three parallel signal channel intended for L, C and X-band of the SAR receiver. The BB is selectable between 50 and 160?MHz bandwidths through switches. The ADC has selectable modes of 5, 6, 7 and 8 bits via control switches. The receiver has a nominal gain of 40 and 37?dB and noise figure of 11 and 13.5?dB for 160?MHz BB filter at room temperature for L-band and C-band, respectively. The circuits, which use a 1.2?V supply voltage, dissipate maximum power of 650?mW with 50?MHz BB and 8 bit mode ADC, and maximum power of 800?mW with 160?MHz BB and 8 bit mode ADC.