A novel ternary JK flip-flop using the resonant tunneling diode literal circuit
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  • 作者:Mi Lin (1)
    Ling-ling Sun (1)
  • 关键词:Resonant tunneling diode (RTD) ; Ternary logic ; Literal circuit ; Module ; 3 operation ; JK flip ; flop ; TN702
  • 刊名:Journal of Zhejiang University - Science C
  • 出版年:2012
  • 出版时间:December 2012
  • 年:2012
  • 卷:13
  • 期:12
  • 页码:944-950
  • 全文大小:563KB
  • 参考文献:1. Berezowski, K.S., Vrudhula, S.B.K., 2005. Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. 8th Euromicro Conf. on Digital System Design鈥擜rchitectures, Methods and Tools, p.139鈥?42. [doi:10. 1109/DSD.2005.21]
    2. Berezowski, K.S., Vrudhula, S.B.K., 2007. Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. Proc. 37th Int. Symp. on Multiple-Valued Logic, p.24鈥?0. [doi:10.1109/ISMVL.2007.36]
    3. Bhattacharya, M., Kulkarni, S., Gonzalez, A., Mazumder, P., 2000. Prototyping Technique for Large-Scale RTD-CMOS Circuits. IEEE Int. Symp. on Circuits and Systems, p.635鈥?38.
    4. Ebata, T., Omae, U., Machida, K., Hoshi, K., Waho, T., 2010. Enhancement of Comparator Operation Speed by Using Negative-Differential-Resistance Devices. Proc. IEEE Int. Symp. on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, p.3020鈥?023. [doi:10.1109/ISCAS.2010.5538003]
    5. Gonz谩lez, A.F., Bhattacharya, M., Kulkarni, S., Mazumder, P., 2001. CMOS implementation of a multiple-valued logic signed-digit full adder based on negative-differential-resistance devices. / IEEE J. Sol. State Circ., 36(6):924鈥?32. [doi:10.1109/4.924855] CrossRef
    6. Guo, W.L., 2009. Resonant Tunneling Devices and Their Applications. Science Press, Beijing, China, p.1鈥?6, 232鈥?34, 350鈥?53 (in Chinese).
    7. Hang, G.Q., Zhou, X.C., 2011. Novel CMOS Ternary Flip-Flops Using Double Pass-Transistor Logic. Int. Conf. on Electric Information and Control Engineering, p.5978鈥?981. [doi:10.1109/ICEICE.2011.5778391]
    8. Homma, N., Saito, K., Aoki, T., 2012. Formal Design of Multiple-Valued Arithmetic Algorithms over Galois Fields and Its Application to Cryptographic Processor. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.110鈥?15. [doi:10.1109/ISMVL.2012.24]
    9. Lee, J., Choi, S., Yang, K., 2010. Implementation of a 4:1 Multiplexing Quantum-Effect IC Based on RTD Circuit Topology. 10th IEEE Conf. on Nanotechnology, p.211鈥?13. [doi:10.1109/NANO.2010.5697741]
    10. Li, X.B., 2009. Digital monolithic integrated circuits based on RTTs. / Micronanoelectr. Technol., 46(1):1鈥? (in Chinese).
    11. Liang, D.S., Gan, K.J., Chun, K.Y., 2010. Frequency Divider Design Using the / 螞-Type Negative-Differential-Resistance Circuit. Proc. 53rd IEEE Int. Midwest Symp. on Circuits and Systems, p.969鈥?72. [doi:10.1109/MWS CAS.2010.5548795]
    12. Lin, M., Sun, Z.Y., Shen, J.Z., 2004. Design of NAND and NOR logic gates based on RTD. / Bull. Sci. Technol., 20(5):434鈥?37 (in Chinese).
    13. Lin, M., L眉, W.F., Sun, L.L., 2007. Design of ternary NAND and NOR gates based on resonant tunneling devices. / J. Semicond., 28(12):1983鈥?987 (in Chinese).
    14. Lin, M., L眉, W.F., Sun, L.L., 2011a. Design of ternary D flip-flop with pre-set and pre-reset functions based on resonant tunneling diode literal circuit. / J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 12(6):507鈥?14. [doi:10. 1631/jzus.C1000222] CrossRef
    15. Lin, M., Zhang, H.P., Sun, L.L., 2011b. Testability Design of Multi-valued RTD Circuits. Int. Conf. on Electronics, Communications and Control, p.510鈥?13. [doi:10.1109/ICECC.2011.6067730]
    16. N煤帽ez, J., Quintana, J.M., Avedillo, M.J., 2007. Correct DC Operation in RTD-Based Ternary Inverters. Proc. 2nd IEEE Int. Conf. on Nano/Micro Engineered and Molecular Systems, p.860鈥?65. [doi:10.1109/NEMS.2007.352154]
    17. N煤帽ez, J., Quintana, J.M., Avedillo, M.J., 2008. Design of RTD-Based NMIN/NMAX Gates. 8th IEEE Conf. on Nanotechnology, p.518鈥?21. [doi:10.1109/NANO.2008.155]
    18. Sasao, T., 2012. Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.185鈥?90. [doi:10.1109/ISMVL.2012.21]
    19. Suzuki, S., Hinata, K., Shiraishi, M., Asada, M., Sugiyama, H., Yokoyama, H., 2010. RTD Oscillators at 430鈥?60 GHz with High Output Power (鈭?00 渭W) Using Integrated Offset Slot Antennas. Int. Conf. on Indium Phosphide and Related Materials, p.152鈥?55. [doi:10.1109/ICIPRM.2010.5516019]
    20. Uemura, T., Baba, T., 2000. Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. Proc. 30th IEEE Int. Symp. on Multiple-Valued Logic, p.305鈥?10. [doi:10.1109/ISMVL.2000.848636]
    21. Wu, H.X., Zhong, S.N., Cai, Q.L., Xia, Q.B., Chen, Y.Y., 2012. Design of quaternary logic circuits based on multiple-valued current mode. / Lect. Notes Electr. Eng., 138:479鈥?88. [doi:10.1007/978-1-4471-2467-2_56] CrossRef
    22. Wu, X.W., 1994. The Design Theory of Multiple Logic Circuits. Hangzhou University Press, Hangzhou, China, p.18鈥?3, 233鈥?61 (in Chinese).
    23. Wu, X.W., Bi, D.X., 1984. Research of the ternary flip-flop based on the module algebra. / Acta Electron. Sin., 12(3):6鈥?3 (in Chinese).
    24. Yuminaka, Y., Okui, M., 2012. Efficient Data Transmission Using Multiple-Valued Pulse-Position Modulation. Proc. IEEE 42nd Int. Symp. on Multiple-Valued Logic, p.7鈥?2. [doi:10.1109/ISMVL.2012.56]
    25. Zhang, W.C., Wu, N.J., 2008. Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs. / Electron. Lett., 44(16):968鈥?69. [doi:10.1049/el:20080507] CrossRef
  • 作者单位:Mi Lin (1)
    Ling-ling Sun (1)

    1. School of Electronics and Information, Hangzhou Dianzi University, Hangzhou, 310018, China
  • ISSN:1869-196X
文摘
A literal circuit with a three-track-output structure is presented based on resonant tunneling diodes (RTDs). It can be transformed conveniently into a single-track-output structure according to the definition and properties of the literal operation. A ternary resonant tunneling JK flip-flop is created based on the RTD literal circuit and the module-3 operation, and the JK flip-flop also has two optional types of output structure. The design of the ternary RTD JK flip-flop is verified by simulation. The RTD literal circuit is the key design component for achieving various types of multi-valued logic (MVL) flip-flops. It can be converted into ternary D and JK flip-flops, and the ternary JK flip-flop can also be converted simply and conveniently into ternary D and ternary T flip-flops when the input signals satisfy certain logical relationships. All these types of flip-flops can be realized using the traditional Karnaugh maps combined with the literal and module-3 operations. This approach offers a novel design method for MVL resonant tunneling flip-flop circuits.

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