Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time \(\Delta \Sigma\) modulator with 15 MHz bandwidth and 60 dB dynamic range

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• 作者：Sakkarapani Balagopal ; Kehan Zhu ; Xinyu Wu…
• 关键词：Analog ; to ; digital converter ; Continuous ; time \(\Delta \Sigma\) ; Digital ; to ; analog converter ; Low ; power single ; bit \(\Delta \Sigma\) ; Tutorial on \(\Delta \Sigma\) ; Testing \(\Delta \Sigma\) ; Board design \(\Delta \Sigma\)
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2017
• 出版时间：March 2017
• 年：2017
• 卷：90
• 期：3
• 页码：625-638
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing;
• 出版者：Springer US
• ISSN：1573-1979
• 卷排序：90

文摘

Continuous-time Delta-Sigma (CT-\(\Delta \Sigma\)) analog-to-digital converters have been extensively investigated for their use in wireless receivers to achieve conversion bandwidths >15 MHz and higher resolution of 10–14 bits. This paper presents the complete design-to-testing tutorial of a state-of-the-art high-speed single-bit CT-\(\Delta \Sigma\) architecture and its circuit design details in 0.13 μm CMOS technology node sampling at 1.25 GS/s. The designed modulator achieves higher dynamic range of 60 dB in a wide conversion bandwidth of 15 MHz and consumes only 3.5 mW. The proposed modulator achieves a Figure of Merit of 154 fJ/level.