Efficient Implementation of 2-D FCT with Reduced Memory Access for Programmable DSPs

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• 作者：Xiangyang Liu (1)
  Hua Bao (2)
  
  1. Department of Computer Science ; Anhui Normal University ; Wuhu ; China
  2. Mobile and Wireless Group ; Broadcom Corporation ; Matawan ; NJ ; USA
  
• 关键词：2 ; D fast cosine transform ; Memory access ; DSP
• 刊名：The Journal of VLSI Signal Processing
• 出版年：2015
• 出版时间：August 2015
• 年：2015
• 卷：80
• 期：2
• 页码：153-161
• 全文大小：577 KB
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• 刊物类别：Engineering
• 刊物主题：Electrical Engineering
  Circuits and Systems
  Computer Imaging, Vision, Pattern Recognition and Graphics
  Computer Systems Organization and Communication Networks
  Signal,Image and Speech Processing
  Mathematics of Computing
  
• 出版者：Springer New York
• ISSN：1939-8115

文摘

In this paper, we present a novel memory access reduction scheme (MARS) for two-dimension fast cosine transform (2-D FCT). It targets programmable DSPs with high memory-access latency. It reduces the number of memory accesses by: 1) reducing the number of weighting factors and 2) combining butterflies in vector-radix 2-D FCT pruning diagram from two stages to one stage with an efficient structure. Hardware platform based on general purpose processor is used to verify the effectiveness of the proposed method for vector-radix 2-D FCT pruning implementation. Experimental results validate the benefits of the proposed method with reduced memory access, less clock cycle and fewer memory space compared with the conventional implementation.