Utilizing Multiple Xeon Phi Coprocessors on One Compute Node
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- 作者：Xinnan Dong (25)
Jun Chai (25)
Jing Yang (25)
Mei Wen (25)
Nan Wu (25)
Xing Cai (26) (27)
Chunyuan Zhang (25)
Zhaoyun Chen (25) - 刊名：Lecture Notes in Computer Science
- 出版年：2014
- 出版时间：2014
- 年：2014
- 卷：8631
- 期：1
- 页码：68-81
- 全文大小：1,160 KB
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Jun Chai (25)
Jing Yang (25)
Mei Wen (25)
Nan Wu (25)
Xing Cai (26) (27)
Chunyuan Zhang (25)
Zhaoyun Chen (25)
25. School of Computer Science, National University of Defense Technology, Changsha, Hunan, 410073, China
26. Simula Research Laboratory, P.O.?Box 134, 1325, Lyakser, Norway
27. Department of Informatics, University of Oslo., P.O.?Box 1080, Blindern, 0316, Oslo, Norway - ISSN：1611-3349
文摘
Future exascale systems are expected to adopt compute nodes that incorporate many accelerators. This paper thus investigates the topic of programming multiple Xeon Phi coprocessors that lie inside one compute node. Besides a standard MPI-OpenMP programming approach, which belongs to the symmetric usage mode, two offload-mode programming approaches are considered. The first offload approach is conventional and uses compiler pragmas, whereas the second one is new and combines Intel’s APIs of coprocessor offload infrastructure (COI) and symmetric communication interface (SCIF) for low-latency communication. While the pragma-based approach allows simpler programming, the COI-SCIF approach has three advantages in (1) lower overhead associated with launching offloaded code, (2) higher data transfer bandwidths, and (3) more advanced asynchrony between computation and data movement. The low-level COI-SCIF approach is also shown to have benefits over the MPI-OpenMP counterpart. All the programming approaches are tested by a real-world 3D application, for which the COI-SCIF approach shows a performance upper hand on a Tianhe-2 compute node with three Xeon Phi coprocessors.