A 60?GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays
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- 作者：Andreas Axholt (1)
Henrik Sj?land (1) - 关键词：CMOS integrated circuits ; Phased arrays ; Millimeter wave integrated circuits ; Receivers
- 刊名：Analog Integrated Circuits and Signal Processing
- 出版年：2014
- 出版时间：July 2014
- 年：2014
- 卷：80
- 期：1
- 页码：23-32
- 全文大小：
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Henrik Sj?land (1)
1. Department of Electrical and Information Technology, Lund University, 22100, Lund, Sweden - ISSN：1573-1979
文摘
This paper presents a front-end architecture for fully integrated 60?GHz phased array receivers. It employs LO-path beamforming using a phase controlled phase-locked loop (PC-PLL). To demonstrate the architecture a circuit is implemented featuring a two stage low noise amplifier, two cascaded active mixers, and a PC-PLL. The receiver downconverts the 60?GHz signal in two steps, using LO signals from the 20?GHz QVCO of the PLL. A differential 2nd-order harmonic is coupled from the sources of the current commutating pairs of the QVCO, feeding the LO-port of the first mixer and downconverting the 60?GHz RF signal to a 20?GHz intermediate frequency. Quadrature 20?GHz LO signals are then used in the second mixer to down-convert the IF signal to baseband. The PLL is locked to a relatively high reference frequency, 1.25?GHz, which reduces the size of the PLL loop filter and enables a compact layout. The measurements show an input return loss better than ?0?dB between 57.5 and 60.8?GHz, a 15?dB voltage gain, and a 9?dB noise figure. Two-tone measurements show ?2.5?dBm IIP3, 29?dBm IIP2, and ?4 dBm ICP1. The PC-PLL phase noise is ?05 dBc/Hz at 1?MHz offset from a 20?GHz carrier, and the phase of the received 60?GHz signal is digitally controllable with a resolution of 3.2°, covering the full 360° range with a phase error smaller than 1°. The chip consumes 80?mA from a 1.2?V supply, and measures 1,400?μm?×?660?μm (900?μm?×?500?μm excluding pads) including LNAs, mixers, and PC-PLL in a 90?nm RF CMOS process.