Analogue feedback inverter based duty-cycle correction

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• 作者：Andreas-Christos Demartinos ; Andreas Tsimpos…
• 关键词：Clock ; Duty ; cycle correction ; Fast ; locked
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2017
• 出版时间：March 2017
• 年：2017
• 卷：90
• 期：3
• 页码：711-716
• 全文大小：
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing;
• 出版者：Springer US
• ISSN：1573-1979
• 卷排序：90

文摘

A simple circuit for duty-cycle correction is proposed in this paper. The configuration is flexible consisting of only three CMOS inverters in a feedback loop. It does not require any reference signal and, therefore, it can be used as a standalone circuit, while it can be applied on a single-ended clock path without breaking the clock line. Simulation results in a 65 nm CMOS technology and 1 V supply voltage give a duty-cycle error less than 1% for a duty-cycle input clock variation between 30 and 70% with a frequency range from 2.4 to 2.9 GHz.