A wideband calibration-free 1.5-GS/s 8-bit analog-to-digital converter with low latency

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• 作者：Fan Jiang ; Danyu Wu ; Lei Zhou ; Yinkun Huang…
• 关键词：ADC ; Folding and interpolating ; Track and hold amplifier ; Folding amplifier ; Binary ; ROM
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2014
• 出版时间：October 2014
• 年：2014
• 卷：81
• 期：1
• 页码：341-348
• 全文大小：1,520 KB
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• 作者单位：Fan Jiang (1)
  Danyu Wu (1)
  Lei Zhou (1)
  Yinkun Huang (1)
  Jin Wu (1)
  Zhi Jin (1)
  Xinyu Liu (1)
  
  1. Institution of Microelectronics, Chinese Academy of Sciences, Beijing, 100029, China
  
• ISSN：1573-1979

文摘

This article presents a wideband calibration-free 8-bit analog-to-digital converter (ADC) with low latency. The ADC employs a two-stage cascaded folding and interpolating architecture. A high-linearity and wideband track-and-hold amplifier combined with a low-parasitic-capacitance folding amplifier is employed to improve the performance. A binary-ROM with “keep-alive-current is proposed to guarantee no miscode when large bit-rate is input. When the sampling frequency is 1.5?GHz, the ADC achieves +0.29/?.20 LSB DNL and 0.90 LSB INL. The ADC’s effective-number-of-bit and spur-free-dynamic-range are 7.0?bit and 51.8?dB respectively at 230?MHz input. The effective-resolution-bandwidth exceeds the second Nyquist zone up to 1.8?GHz. All of this makes this ADC suitable for wideband digital receiver system.