A sideband-suppressed fast-hopping synthesizer for dual-carrier OFDM UWB transceivers

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• 作者：Haipeng Fu (1)
  Deyun Cai (1)
  Danfeng Chen (1)
  Junyan Ren (1) (2)
  Wei Li (1)
  Ning Li (1)
  
• 关键词：I/Q calibration ; UWB ; Dual carrier ; Sideband rejection ; CMOS
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2013
• 出版时间：March 2013
• 年：2013
• 卷：74
• 期：3
• 页码：557-568
• 全文大小：1298KB
• 参考文献：1. IEEE802.15.3. (2003). High rate alternative PHY task group (TG3a) for wireless personal area networks (WPANS), IEEE802.15.3. (2003). http://www.ieee802.org/15/pub/TG3a.html.
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  15. Lanka, N. R., Patnaik, S. A., & Harjani, R. A. (2011). Frequency-hopped quadrature frequency synthesizer in 0.13-μm technology. / IEEE Journal of Solid-State Circuits, / 46(9), 2021-032. CrossRef
  
• 作者单位：Haipeng Fu (1)
  Deyun Cai (1)
  Danfeng Chen (1)
  Junyan Ren (1) (2)
  Wei Li (1)
  Ning Li (1)
  
  1. State Key Laboratory of ASIC and System, Fudan University, Shanghai, China
  2. Micro-/Nano-Electronics Science and Innovation Platform, Fudan University, Shanghai, China
  
• ISSN：1573-1979

文摘

A sideband-suppressed China UWB Standard synthesizer which is able to generate two carriers simultaneously is presented. An efficient synthesizing technique with a single quadrature phase-locked loop (QPLL) is proposed for fast band switching. To suppress accumulating sidebands at the outputs, a clock buffer with I/Q calibration and distortion cancellation technique is proposed. Fabricated in TSMC 0.13-μm CMOS technology and operated at 1.2?V, the synthesizer measures a maximum sideband rejection of 45?dB and a phase noise of ?05 dBc/Hz at 1-MHz offset. The synthesizer covers frequency range from 6.2 to 9.4?GHz with band switching time less than 1.4?ns.