A highly linear CMOS transconductance amplifier in 180?nm process technology

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• 作者：Sougata Kumar Kar (1) sougatakar@ee.iitkgp.ernet.in
  Siddhartha Sen (1) ssen@ee.iitkgp.ernet.in
• 关键词：Transconductance amplifier – Linearization – Harmonic distortion – Noise
• 刊名：Analog Integrated Circuits and Signal Processing
• 出版年：2012
• 出版时间：July 2012
• 年：2012
• 卷：72
• 期：1
• 页码：163-171
• 全文大小：357.7 KB
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• 作者单位：1. Department of Electrical Engineering, Indian Institute of Technology, Kharagpur, India
• 刊物类别：Engineering
• 刊物主题：Circuits and Systems
  Electronic and Computer Engineering
  Signal,Image and Speech Processing
  
• 出版者：Springer Netherlands
• ISSN：1573-1979

文摘

The present article describes the design and analysis of an operational transconductance amplifier (voltage to current converter) with wide linear input range. The proposed configuration combines the techniques of signal attenuation and source degeneration in order to reduce the odd order harmonic distortion significantly. The proposed circuit is compared with several circuit topologies based on MOS differential pairs with respect to their achievable linearity, input referred noise and power consumption. The linear transconductor is designed and simulated in 180 nm CMOS process technology with 1.8 V power supply. Simulation results show third order harmonic distortion (HD ₃) of ?70 dB for 600 mV_pp input signal. For 1% transconductance variation the linear range is about 1.2 V_pp. The input referred noise of the transconductor is 70 nV/?{\text Hz}70\,\hbox{nV}/\sqrt{\text {Hz}} at 10 MHz. The quiescent power consumption is only 450 μW.