An area-and-power-efficient 8.4-bit ENOB 30 MS/s SAR ADC in 65 nm CMOS
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- 作者：Ye Xu ; Pieter Harpe ; Trond Ytterdal
- 关键词：Analog ; to ; digital converter (ADC) ; Successive approximation register (SAR) ; Ultrasound imaging systems ; Power efficiency ; Area efficiency
- 刊名：Analog Integrated Circuits and Signal Processing
- 出版年：2017
- 出版时间：January 2017
- 年：2017
- 卷：90
- 期：1
- 页码：17-27
- 全文大小：
- 刊物类别：Engineering
- 刊物主题：Circuits and Systems; Electrical Engineering; Signal,Image and Speech Processing;
- 出版者：Springer US
- ISSN：1573-1979
- 卷排序：90
文摘
Area and power consumption are two main concerns for the electronics towards the digitalization of in-probe 3D ultrasound imaging systems. This work presents a 10-bit 30 MS/s successive approximation register analog-to-digital converter, which achieves good area efficiency as well as power efficiency, by using a symmetrical MSB-capacitor-split capacitor array with customized small-value finger capacitors. Moreover, simplified dynamic digital logic and a dynamic comparator have been designed. Fabricated in a 65 nm CMOS technology, the core circuit only occupies 0.016 mm2. The ADC achieves a signal-to-noise ratio of 52.2 dB, and consumes 61.3 μW at 30 MS/s from a 1 V supply voltage, resulting in a figure of merit (FoM) of 6.2 fJ/conversion-step. The FoM defined by including the area is 0.1 mm2 fJ/conversion-step.