Improving Performance,Power Efficiency,Yield,and Reliability Using Programmable Power-gating Techniques.

详细信息   

• 作者：Sinkar ; Abhishek Arvind.
• 学历：Doctor
• 年：2012
• 导师：Kim,Nam Sung,eadvisorCompton,Katherineecommittee memberSankaralingam,Karthikeyanecommittee memberLipasti,Mikko H.ecommittee memberSaluja,Kewal K.ecommittee member
• 毕业院校：The University of Wisconsin
• Department：Electrical Engineering.
• ISBN：9781267615732
• CBH：3527346
• Country：USA
• 语种：English
• FileSize：1695646
• Pages：162

文摘

Power-gating (PG) is commonly used in multi-core processors to reduce standby leakage power of cores. By controlling the strength of the PG device,it is possible to control the performance and power consumption of the connected core in active mode. Techniques to improve performance,yield,power efficiency,and reliability of multi-core processors by tuning the PG device strength while exploiting process variations are presented. Our proposed post-silicon PG tuning technique improves yield by recovering most leaky dies when die-to-die variations are considered. When the tuning is applied to per-core PG in presence of within-die variations,it improves the die FMAX by up to 21%. PG device is often sized to consider the PG device aging and worst-case current at high temperature. This results in higher than necessary active leakage in early chip lifetime and/or lower temperatures. Two techniques are proposed to adjust the strength of a PG device based on its aging and IC's temperature at runtime and reduce both dynamic and active leakage power by up to 3.7% and 10% in early chip lifetime. These techniques also reduce the gate-oxide failure rate by up to 5%. Adaptive voltage scaling (AVS) is used to mitigate the impact of process variations in power-constrained processors. A methodology is proposed that optimizes both the size of PG device and the degree of AVS jointly such that PG size is minimized while maximizing power efficiency. Simulation results demonstrate that the joint optimization,considering both die-to-die and within-die variations,reduces the size of PG device by more than 50% with 3% frequency improvement for power-constrained multi-core processors. A cost-effective method to implement on-die,per-core voltage regulators (VRs) using per-core PG devices is also proposed. Simulation results show that processors using this technique can achieve power efficiency as high as those using per-core on-chip switching VRs at much lower cost. Finally,for multi-core processors with per-core voltage/frequency domains,an optimization method is presented which maximizes the performance by balancing the power of fast and slow cores. The proposed optimization reduces thermal throttling of fast cores in power/thermal-constrained multi-core processors and improves throughput by up to 10%.