文摘
Trends in microarchitecture, reliability, and devices are precipitating accelerated exploration of new architectural approaches. These rapid changes necessitate tools to rapidly evaluate new architectural ideas on specific benchmarks. We observe that previous work in models has focused on either models for architectural flexibility or accuracy. In this dissertation, we develop three modeling approaches that explore the trade-off between architectural flexibility and accuracy for CPUs and GPUs. First, we develop an upper-bound model to use in design space exploration to find the impact of power, area, and performance trade-offs as power and area change at different rates to aid in resource planning for multicores. Second, we refine previously developed custom core models to accurately predict performance on hardware to understand performance bottlenecks and facilitate expansion of those models to incorporate microarchitectural changes. Finally, we develop an approach to predict a new architecture's performance using data collected on another architecture without developing code for the second architecture would be even more useful for cases where the second architecture is not yet available or the programmer overhead to convert code is high. Through these three approaches, we find new possibilities for modeling in the architectural flexibility and accuracy trade-off space.