Reusable OpenCL FPGA Infrastructure.

详细信息   

• 作者：Chin ; S. Alexander.
• 学历：Master
• 年：2012
• 导师：Chow,Paul,eadvisor
• 毕业院校：University of Toronto
• Department：Electrical and Computer Engineering.
• ISBN：9780494856611
• CBH：MR85661
• Country：Canada
• 语种：English
• FileSize：677171
• Pages：71

文摘

OpenCL has emerged as a standard programming model for heterogeneous systems. Recent work combining OpenCL and FPGAs has focused on high-level synthesis. Building a complete OpenCL FPGA system requires more than just high-level synthesis. This work introduces a reusable OpenCL infrastructure for FPGAs that complements previous work and specifically targets a key architectural element&mdash；the memory interface. An ＜italic＞Aggregating Memory Controller ＜/italic＞ that aims to maximize bandwidth to external,large,high-latency,high-bandwidth memories and a template Processing Array with soft-processor and hand-coded hardware elements are designed,simulated,and implemented on an FPGA. Two micro-benchmarks were run on both the soft-processor elements and the hand-coded hardware elements to exercise the Aggregating Memory Controller. The micro-benchmarks were simulated as well as implemented in a hardware prototype. Memory bandwidth results for the system show that the external memory interface can be saturated and the high-latency can be effectively hidden using the Aggregating Memory Controller.