Network-on-Chip virtualization in Chip-Multiprocessor Systems

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• 作者：Francisco Triviñ ; o^a ; ^{ftrivino@dsi.uclm.es}  ; [Author Vitae] ; Jos&eacute ; L. Sá ; nchez^a ; ^{jsanchez@dsi.uclm.es}  ; [Author Vitae] ; Francisco J. Alfaro^a ; ^{falfaro@dsi.uclm.es}  ; [Author Vitae] ; Jos&eacute ; Flich^b ; ^{jflich@disca.upv.es}  ; [Author Vitae]
• 关键词：Chip Multiprocessor ; Network-on-Chip ; Virtualization
• 刊名：Journal of Systems Architecture
• 出版年：2012
• 期刊代码：81_13837621
• 类别：cp
• 出版时间：March, 2012
• 卷：58
• 期：3-4
• 页码：126-139
• 文件大小：1147 K

摘要

It is expected that Chip Multiprocessor Systems (CMPs) will contain more and more cores in every new generation. However, applications for these systems do not scale at the same pace. In order to obtain a good CMP utilization several applications will need to coexist in the system and in those cases virtualization of the CMP system will become mandatory. In this paper we analyze two virtualization strategies at NoC-level aiming to isolate the traffic generated by each application to reduce or even eliminate interferences among messages belonging to different applications. The first model handles most interferences among messages with a virtual-channels (VCs) implementation reducing both execution time and network latency. However, using VCs results in area and power overhead due to the cost of control and buffer implementation. In contrast, the second model is based on the resource partitioning strategies which results in a space partitioning of the CMP chip in several regions. For this last model, Virtual-Regions (VR), we use a reconfiguration algorithm of the network that is able to dynamically adapt the network partitions in order to satisfy the application requirements. The paper shows a comparison of both models and identifies their main advantages and disadvantages. From our experimental results, we show that our proposal obtains in terms of execution time average improvements of 30%for parallel applications when compared to a baseline scenario. Moreover, when compared to a VCs implementation, our proposal improves the average execution time by 9%for parallel applications.