Computation and power reduction techniques for H.264 intra prediction

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• 作者：Yusuf Adibelli ; ^{yadibelli@sabanciuniv.edu}  ; [Author Vitae] ; Mustafa Parlak ^{mparlak@sabanciuniv.edu}  ; [Author Vitae] ; Ilker Hamzaoglu ^{hamzaoglu@sabanciuniv.edu}  ; [Author Vitae]
• 关键词：H.264 ; Intra prediction ; Low power ; Hardware implementation ; FPGA
• 刊名：Microprocessors and Microsystems
• 出版年：2012
• 期刊代码：129_01419331
• 类别：et
• 出版时间：May, 2012
• 卷：36
• 期：3
• 页码：205-214
• 文件大小：442 K

摘要

H.264 intra prediction algorithm has a very high computational complexity. In this paper, we propose pixel equality and pixel similarity based techniques for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware. These techniques exploit pixel equality and similarity in a video frame by performing a small number of comparisons among pixels used in prediction equations before the intra prediction process. If the pixels used in prediction equations are equal or similar, prediction equations simplify significantly. By exploiting the equality and similarity of the pixels used in prediction equations, the proposed pixel equality and pixel similarity based techniques reduce the amount of computations performed by 4 脳 4 intra prediction modes up to 78%and 89%, respectively, with a small comparison overhead. We also implemented an efficient 4 脳 4 intra prediction hardware including the proposed techniques using Verilog HDL. The proposed pixel equality and pixel similarity based techniques reduced the power consumption of this hardware up to 13.7%and 17.2%, respectively. The proposed pixel equality based technique does not affect the PSNR and bitrate. The proposed pixel similarity based technique increases the PSNR slightly for some videos frames and it decreases the PSNR slightly for some videos frames.