Temperature dependent drain current model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range

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• 作者：Vandana Kumari^a ; ^{vandanakumari511@gmail.com} ; Manoj Saxena^b ; ^{saxena_manoj77@yahoo.co.in} ; R.S. Gupta^c ; ^{rsgu@bol.net.in} ; Mridula Gupta^a ; ^{mridula@south.du.ac.in}
• 刊名：Microelectronics Reliability
• 出版年：2012
• 期刊代码：128_00262714
• 类别：et
• 出版时间：June, 2012
• 卷：52
• 期：6
• 页码：974-983
• 文件大小：1475 K

摘要

This paper presents two dimensional temperature dependent analytical model of Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET and compares it with the simulated data using ATLAS 3D device simulator for wide operating temperature i.e. 300-500 K for channel length down to 32 nm technology node. In this work, a temperature dependent analytical expression of drain current for sub-threshold region to saturation region has been developed. Lower sub-threshold slope and reduced leakage current in case of ISESON MOSFET (as compared to ISE and SON) results in better NMOS inverter performance and hence ISESON can be widely used in CCD camera as well as for fast switching applications. Further, we have also investigated the impact of temperature on electrical characteristics of ISESON MOSFET which are important for analog applications.