On development of 6H-SiC LDMOS transistors using silane-ambient implant anneal

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• 作者：Sankin ; I. ; Casady ; J.B. ; Dufrene ; J.B. ; Draper ; W.A. ; Kretchmer ; J. ; Vandersand ; J. ; Kumar ; V. ; et. al.
• 关键词：Silicon carbide ; LDMOS ; Power switch ; Transistor ; MOSFET
• 刊名：Solid-State Electronics
• 出版年：2001
• 期刊代码：73_00381101
• 类别：ph
• 出版时间：September, 2001
• 卷：45
• 期：9
• 页码：1653-1657
• 文件大小：550 K

摘要

6H-SiC lateral double implanted metal oxide semiconductor field effect transistors have been fabricated on four p-type wafers with p-type epitaxial layers doped with Al at 2–7×10¹⁶ cm⁻³. Each of the wafers received two nitrogen implants of heavy and light doses for drain/source and drift regions, respectively. The wafers had the implants activated at 1600°C in an Ar ambient (one wafer) or a silane overpressure ambient (three wafers). The subsequent characterization confirmed a much smoother surface for the silane-annealed wafers, with step bunching reduced from 25 nm peak steps with periodicity of 1 μm to undetectable steps. Near optimal breakdown voltages of 600 V were obtained for a 9 μm drift region length devices, and threshold voltage ranged from 9 to 12 V. Average values for effective channel mobility μ_eff were in the range 35.2–44.1 cm²/Vs for the three silane-annealed wafers, and 30.0 cm²/Vs for the argon-annealed wafer.