Reconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device

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• 作者：Ka Fai Cedric Yiu^a ; ^{macyiu@polyu.edu.hk}  ; [Author Vitae] ; Yao Lu^a  ; [Author Vitae] ; Chun Hok Ho^b  ; [Author Vitae] ; Wayne Luk^b  ; [Author Vitae] ; Jiaquan Huo^c  ; [Author Vitae] ; Sven Nordholm^c  ; [Author Vitae]
• 关键词：Echo cancellation ; Double-talk ; FPGA ; Voice control ; Speech recognition
• 刊名：Digital Signal Processing
• 出版年：2012
• 期刊代码：128_10512004
• 类别：cp
• 出版时间：March, 2012
• 卷：22
• 期：2
• 页码：376-390
• 文件大小：1337 K

摘要

Acoustic echo control is of vital interest for hands-free operation of telecommunications equipment. An important property of an acoustic echo canceller is its capability to handle double-talk and be able to operate in real time. When it is applied to intelligent voice control device, it is important to suppress the speech from the device and enhance the speech of the user for speech recognition, where double-talk situation is frequently occurred. In this paper, we propose a novel hardware architecture to support a robust adaptive algorithm in combination with a switching path model to tackle the double-talk situation. The proposed switching path model avoids adapting two filters at the same time during double-talk and prevents the disadvantage of the conventional two-path model. In order to achieve computational efficiency and to meet the rigorous timing requirements, the echo canceller is operated in the frequency domain and its computing power is raised by a hardware accelerator implemented in the FPGA fabric surrounding a PowerPC on a Xilinx XUP V2P platform. Results obtained show the echo canceller is successful in handling double-talk situation and the sub-band implementation has improved convergence significantly. An overall improvement by 82.5 times is achieved when a hardware accelerator is used to perform the critical part of the algorithm over a pure software implementation running on a 300 MHz embedded PowerPC processor.