A fast MPSoC virtual prototyping for intensive signal processing applications

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• 作者：Rabie Ben Atitallah^a ; ^{Rabie.Ben-Atitallah@lifl.fr}  ; [Author Vitae] ; É ; ric Piel^b ; ¹ ; ^{e.a.b.piel@tudelft.nl}  ; [Author Vitae] ; Smail Niar^a ; ² ; ^{smail.niar@univ-valenciennes.fr}  ; [Author Vitae] ; Philippe Marquet^c ; ³ ; ^{Philippe.Marquet@lifl.fr}  ; [Author Vitae] ; Jean-Luc Dekeyser^c ; ⁴ ; ^{jean-luc.dekeyser@lifl.fr}  ; [Author Vitae]
• 关键词：MPSoC ; Model of computation ; Model of execution ; Simulation ; Transaction level modeling ; Virtual processor
• 刊名：Microprocessors and Microsystems
• 出版年：2012
• 期刊代码：129_01419331
• 类别：et
• 出版时间：May, 2012
• 卷：36
• 期：3
• 页码：176-189
• 文件大小：1559 K

摘要

Due to the growing computation rates of intensive signal processing applications, using Multiprocessor System on Chip (MPSoC) becomes an incontrovertible solution to meet the functional requirements. Today, Electronic System Level (ESL) design is considered a vital premise to overcome the design complexity intrinsic in the heterogeneity of these devices. However, the development of tools at the system level is in the face of extremely challenging requirements such as the rapid system prototyping, the accurate performance estimation, and the reliable design space exploration (DSE).

Focusing on the issue of ESL development tools, this paper describes an MPSoC environment design which targets the Multidimensional Intensive Signal Processing (MISP) application domain. Within this environment, we have defined first a generic execution model that supports any type of MPSoC. It can adapt to any parallel application and handle efficiently the scheduling and synchronizations at all the levels of granularity. Second, a new Virtual Processor (VP) based simulation technique is proposed for implementing the execution model. This proposal leverages the high-level specification of the system to provide a heterogeneous MPSoCs simulation without using an Instruction Set Simulator (ISS). VP-based simulation is implemented in SystemC at a timed transactional level allowing a good trade-off between high simulation speed and performance estimation accuracy. The usefulness and the effectiveness of our MPSoC environment is illustrated through two MISP applications executed on a typical MPSoC. Results show that our approach enables fast MPSoC virtual prototyping, data transfers and timing analysis, and reliable DSE for architectural optimizations.