Shared hardware, high throughput implementation of 2D 4 脳 4 and 8 脳 8 integer transform for H.264/AVC high-profile coders

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• 作者：Honey Durga Tiwari ^{honeyndt@konkuk.ac.kr} ; Meeturani Sharma¹ ; ^{meetundt@konkuk.ac.kr} ; Yong Beom Cho² ; ^{ybcho@konkuk.ac.kr}
• 关键词：DCT ; Dual clock architecture ; H.264/AVC ; IDCT ; Integer transform ; Low cost ; Resource sharing
• 刊名：AEU - International Journal of Electronics and Communications
• 出版年：2012
• 期刊代码：1_14348411
• 类别：cp
• 出版时间：July, 2012
• 卷：66
• 期：7
• 页码：521-531
• 文件大小：978 K

摘要

Two-dimensional discrete cosine transforms are used in the core transformations in all profiles of the H.264/Advanced video coding (AVC) standard. In this paper, implementing the resource sharing of high throughput 4 脳 4 and 8 脳 8 forward and inverse integer transforms for high definition H.264 is presented. It is shown that the 4 脳 4 forward/inverse transform can be obtained from 8 脳 8 forward/inverse transform using selective data input and data arrangement at intermediate stages. Fast 8 脳 8 forward and inverse transform is implemented using matrix decomposition and matrix operation such as Kronecker product and direct sum. The proposed implementation does not require any transpose memory and has a dual clocked pipeline structure. Compared with existing designs, the gate count is reduced by 27.7%in the proposed design. The maximum operating frequency of the proposed system is approx. 1.3 GHz, while the throughput is 7 G and 18.7 G pixels/s for 4 脳 4 and 8 脳 8 forward integer transforms, respectively. The proposed design can be used for real time H.264/AVC high definition processing owing to its high throughput and low hardware cost.