Electrical characteristics of 20-nm junctionless Si nanowire transistors

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• 作者：Chan-Hoon Park^a ; ^{chpark82@postech.ac.kr} ; Myung-Dong Ko^a ; Ki-Hyun Kim^a ; Rock-Hyun Baek^a ; Chang-Woo Sohn^a ; Chang Ki Baek^e ; Sooyoung Park^e ; M.J. Deen^c ; ^d ; Yoon-Ha Jeong^a ; ^b ; ^c ; ^e ; Jeong-Soo Lee^a ; ^b ; ^c ; ^{ljs6951@postech.ac.kr}
• 关键词：Junctionless transistor ; Nanowire transistor ; Multigate ; Short channel characteristics ; Subthreshold slope ; Drain induced barrier lowering
• 刊名：Solid-State Electronics
• 出版年：2012
• 期刊代码：73_00381101
• 类别：ph
• 出版时间：July, 2012
• 卷：73
• 期：Complete
• 页码：7-10
• 文件大小：802 K

摘要

We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20-250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 nm showed excellent electrical characteristics with a high I_on/I_off ratio (>10⁶), good subthreshold slope (鈭?9 mV/dec), and low drain-induced barrier lowering (鈭?0 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes.