Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)
- 作者：Xiaowu Zhang ; Vaidyanathan Kripesh ; T.C. Chai ; Teck Chun Tan ; D. Pinjala
- 关键词：Starch ; Activated carbon ; Pore structure ; Electric double layer capacitor ; Electrochemical properties
- 刊名：Microelectronics Reliability
- 出版年：2008
- 期刊代码：128_00262714
- 类别：et
- 出版时间：April 2008
- 卷：48
- 期：4
- 页码：602-610
- 文件大小：1676 K
摘要
Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4 mm pitch Cu post type WLP has been developed for mobile computing application. The Cu post type WLP has 440 I/Os and 12 × 12 mm die size. The initial design WLP has been fabricated and subjected to a thermal cycling (TC) testing. The failure life of the original WLP under TC was 296 cycles. This paper also presents a nonlinear finite element analysis of the board level solder joint reliability and methods for enhancement of the WLP. A viscoplastic constitutive relation is adopted for the solder joints to account for its time and temperature dependence in TC. The fatigue life of the solder joint is estimated by the modified Coffin–Manson equation. The two coefficients in the modified Coffin–Manson equation are also determined. A series of parametric studies are performed by changing the passivation (PI) thickness, redistribution layer (RDL) thickness, polymer height (Cu post height accordingly varies), die thickness, PCB thickness, and PCB CTE. The results obtained from the modeling are useful to formulate design guidelines for board level reliability enhancement of the WLP.