This paper addresses on
VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC
![Click to view the MathML source](http://www.sciencedirect.com/cache/MiamiImageURL/B6V1M-4NT84HW-1-38/0?wchp=dGLbVlz-zSkzS)
1P6M technology. As shown in the result of physical implementation, the core size is
![Click to view the MathML source](http://www.sciencedirect.com/cache/MiamiImageURL/B6V1M-4NT84HW-1-3N/0?wchp=dGLbVlz-zSkzS)
and the VLSI implementation of ROF can operate at 256 MHz for 1.8 V supply.