Exact custom instruction enumeration for extensible processors
- 作者：Chenglong Xiao ; chenglong.xiao@irisa.fr ; [Author Vitae] ; Emmanuel Casseau emmanuel.casseau@irisa.fr ; [Author Vitae]
- 关键词：Extensible processors ; ASIPs ; DFG ; Custom instruction ; Custom instruction generation algorithm
- 刊名：Integration ; the VLSI Journal
- 出版年：2012
- 期刊代码：71_01679260
- 类别：et
- 出版时间：June, 2012
- 卷：45
- 期：3
- 页码：263-270
- 文件大小：974 K
摘要
In recent years, the use of extensible processors has been increased. Extensible processors extend the base instruction set of a general-purpose processor with a set of custom instructions. Custom instructions that can be implemented in special hardware units make it possible to improve performance and decrease power consumption in extensible processors. The key issue involved is to generate and select automatically the custom instructions from a high-level application code. In this paper, we propose a new efficient algorithm for the automatic generation of all candidate instructions (or patterns). Our pattern generation algorithm identify all feasible connected and disjoint patterns under different constraints. Compared to a previously proposed well-known algorithm, our algorithm solves the problem more efficiently by taking advantage of the topological property of data flow graph (DFG) as well as overcoming the drawbacks of the previously proposed algorithm. An extension of the proposed algorithm is also presented in this paper. The extended algorithm further radically reduce the search space by considering the input resolving nodes. Experimental results show that our algorithms can achieve orders of magnitude speedup over the well-know algorithm.